Product Tour: CHAMP-FX4 6U OpenVPX FPGA Processing Module
November 12, 2014
Access high-end FPGA processing for ISR Systems
To get the mission-critical performance demanded by today's ISR systems, you need modules with dedicated processing power, balanced with fast memory and Gen3 interconnects that deliver 40 Gigabits per second.
Curtiss-Wright's 6U OpenVPX CHAMP-FX4 FPGA Processor Card is built to reliably meet these requirements, even under the harshest conditions. The video outlines the board's design and then shows live signal integrity testing, with resulting Eye Diagrams.
The CHAMP-FX4 6U OpenVPX Module Features
- Three Xilinx Virtex-7 FPGAs
- Each one executing 5 billion multiply-accumulate ops/s
- Gen3 PCIe or Gen2 SRIO
- 12 GB SDRAM
- 40 Backplane SERDES Lines @ 10Gbps
- Two FMC sites
- Xilinx ZYNQ FPGA Dual ARM Core Processor
Designed with Fabric40™ Technology for Gen3 Fabrics
The CHAMP-FX4 uses Fabric40 technology to overcome the signal integrity issues of OpenVPX at 10+ Gbaud signaling. It supports the latest high-speed 40 Gbps fabrics for high-performance radar processing, SIGINT and EO/IR systems that cannot afford to compromise on performance.
The CHAMP-FX4's Video Transcript for Visual and Hearing Impaired
From Missile defense radar to signal intelligence and EO/IR, failure is not an option. To get the mission-critical performance demanded by today's ISR systems, you need modules with dedicated processing power, balanced with fast memory and Gen3 interconnects that deliver 40 Gigabits per second. Curtiss-Wright's 6U OpenVPX CHAMP-FX4 is built to reliably meet these requirements, even under the harshest conditions.
The CHAMP-FX4 is powered by three units of cutting-edge silicon, the Xilinx Virtex-7 FPGA. It is a DSP processor dynamo that executes an impressive 5 billion Multiply-Accumulate operations per second. Supported by abundant memory and multiple flexible, high-bandwidth I/O interfaces-?including two FMC sites-?this is balanced high-performance you can count on when it matters most.
The performance of the CHAMP-FX4 is a building block for extremely powerful, OpenVPX deployable systems, air- or conduction-cooled, using Gen2 Serial RapidIO or the new Gen3 PCIe protocol. However, signal integrity is a major technical challenge for OpenVPX systems operating at Gen3 bandwidths. The OpenVPX connector standard was designed to support signaling rates up to 6.25 Gigabaud. Running Gen3 fabrics means pushing that connector to 10+ Gigabaud. An Eye Diagram, showing the amount of signal distortion, is almost closed when an OpenVPX connector is pushed to 10 Gigabaud. Curtiss-Wright overcomes these signal integrity problems with Fabric40 Technology. Backplanes, chassis and boards, like the CHAMP-FX4, use Fabric40 design rules to create systems that run effectively at Gen3 speeds.
Here in the lab, the CHAMP-FX4 is running IBERT testing software from Xilinx, which operates all of its 10.3 Gigabit per second SERDES lines in parallel, going through a mixture of pathways, including the backplane, cables and on-board connections. This testing validates signal integrity on all the individual lines, as well as insuring that there are no power supply or cross talk issues. And Open Eye diagrams clearly demonstrate the high levels of signal integrity maintained by the CHAMP-FX4 - signal integrity that guarantees system reliability. The CHAMP-FX4 harnesses the computing power of three Virtex-7 FPGAs for deployable embedded processing systems Delivering market-leading performance for new OpenVPX Gen3 40 Gigabit-per-second systems, And using Fabric40 technology to overcome OpenVPX signal integrity limitations When performance matters most, the CHAMP-FX4 delivers.