Delivering Signal Integrity with High-performance FPGAs & Gen3 Bandwidths
April 08, 2015 | BY: Denis SmetanaDownload PDF
System designers using powerful new FPGAs for ISR applications face signal integrity challenges within the OpenVPX standard. Curtiss-Wright has developed Fabric40 Technology to meet the challenge and deliver flawless execution at Gen3 signaling rates. This white paper discusses the issues and then presents extensive details from signal integrity testing that prove the effectiveness of Fabric40 Technology.
Powerful FPGAs Must Be Balanced with High-bandwidth I/O
ISR system designers are expanding their use of FPGAs, which now deliver tremendous levels of DSP performance. For example, Xilinx Virtex-7 devices can support approximately five billion multiply-accumulate operations per second when factoring in clock frequency. With this kind of processing power, FPGAs can execute the required level of complex calculations – but they must also be designed into modules that have the I/O bandwidth to move those data streams into and out of the FPGAs, keeping the processor engines fed with data. For many rugged applications, the form factor of choice is OpenVPX due to its ability to support high interconnect bandwidths and operate in rugged environments.
Two common design scenarios have I/O demands that translate into multiple high-speed serializer/deserializer (SerDes) lines connecting to each FPGA.
- Beamforming operations for large radar applications, using multiple FPGA modules interconnected by SerDes lines so they can process the interactions of many hundreds or even thousands of sensors.
- FPGAs that accept SerDes input directly from high bandwidth analog conversion front ends. As sampling rates and resolution increase, the amount of data per sensor stream multiplies.
Today’s largest FPGAs have 36, 72 or more SerDes lines, each of which is capable of running at Gen3 bandwidths of over 10 Gbps.