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Introduction to Hypervisor Technology

February 15, 2013

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With the emergence in recent years of multi-core processors, a breakthrough computing innovation that promises to deliver higher performance without drastically increasing power, the embedded military industry finds itself in a new era of great potential, rife with system design choices never before available to software designers. In the early days of multi-core, which originated in dual core architectures, operating system (OS) designers didn't know yet how to optimally leverage the processing potential of this promising new chip architecture. What's more, software architects often struggled to understand why their applications, originally designed for a classic single core processor, would actually perform slower on the new multi-core technology. Today, operating systems are much more sophisticated: they've evolved along with the multi-core technology which now frequently incorporates 4, 8 or 16 cores, and can now be leveraged by architects to harness the full processing power contained in contemporary multiple core offerings.

The first efforts to exploit the potential of multi-core processors involved the use of Symmetrical Multi Processing (SMP). SMP emerged early as a popular way to evolve traditional single core applications to be able to take advantage of all available cores. With SMP all of the processor's cores are controlled by a single OS. While this approach had advantages, the use of a single operating system was also found to be a serious limitation. For example, in the case where the application had hard real-time requirements as well as HMI (Human Machine Interface) and/or control requirements, SMP resulted in a Real Time Operating System (RTOS) being overkill for the HM, while the standard operating system would be unable to manage the application's real-time requirements.

In the previous example the ideal solution is to run two individual operating systems - one tailored for the real-time requirements and one designed for system management. Before the advent of multi-core processors along with the operating systems designed to fully support them, the typical solution would have required an Asymmetrical Multiprocessor (AMP) architecture in which two individual physical processors are placed on a board, each with physically separated memory and hardware resources. In this AMP approach each processor would run a separate copy of its required operating systems. AMP continues to be appropriate for some system designs in High Performance Embedded Computing (HPEC) applications, but today they are both costly and too complex to use in classic Single Board Computer (SBC) applications. Today, with the quad-core Intel® Core™ i7 and associated bridge, memory and hardware, it's possible to design a SBC with multi-core processors and run multiple operating systems. The key element that makes it possible to move from older AMP designs to now fully leverage the potential of multi-core processors is Hypervisor.

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