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Optimizing Performance in OpenVPX Architectures With Intel Xeon Processors

January 03, 2018 | BY: Marc Couture

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OpenVPX (VITA 65) has made the VPX architecture a preferred option for modules and subsystems engineered for defense industry applications. Many OpenVPX solutions have been deployed since the standard was ratified in 2010 and continue to perform admirably in rugged and very demanding land, air, and sea environments. Today, multicore processors, such as the server-class Intel Xeon family of processors, provide more compute power for a variety of 3U and 6U OpenVPX solutions. System designers are turning to these powerful processors to meet demanding application requirements where high performance and standards-based form factors are needed

However, the choice of Xeon processor can have a significant impact on the size, weight, power, and cost (SWaP-C) associated with each module, as well as subsystem complexity and overall reliability. Designers considering Intel’s Xeon E5 or the Xeon D System on Chip (SoC) should look beyond teraflops (TFLOPs) per slot capabilities and weigh the pros and cons of each device to ensure they get the optimal balance of performance, complexity, cost, and reliability in their subsystem architecture.

Figure 1: Xeon processor choice impacts SWaP-C and overall solution complexity

Download this Optimizing Performance in OpenVPX Architectures With Intel Xeon white paper to learn more about

  • Intel Xeon Processor family comparisons
  • Processor selection criteria trade-offs
  • Module design complexity considerations
  • Creating balanced and high reliability solutions

Author’s Biography

Marc Couture

Senior Product Manager for Intel, Power Architecture, and GPGPU based Digital Signal Processors

Marc Couture is the Senior Product Manager for Intel, Power Architecture, and GPGPU based Digital Signal Processors in the ISR Solutions group at Curtiss-Wright. He has worked in the Embedded COTS industry for over 20 years having specialized in High Performance Embedded Computing and RF/Microwave technologies. Marc is a graduate of the University of Massachusetts Dartmouth with a Masters of Science in Electrical Engineering.

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