Scale Down Rugged Mission Computers…and Still Boost Performance?

Electronic Design

Published in Electronic Design

The Xeon-D SoC has more cores and threads per CPU (up to 16 cores/32 threads), helping designers upgrade mission computers without the SWaP concerns.

A key consideration for system designers looking to enhance their platform’s mission computers, or add new processing or I/O capabilities, is how best to boost resources without piling on unmanageable size, weight, and power (SWaP) burdens. For some time now, designers of Intel processor-based commercial-off-the-shelf (COTS) embedded systems have leveraged PCIe bus interfaces when developing mission processors.

One challenge that system designers have had to contend with is the limited number of PCIe lanes supported by traditional mobile-class CPU architectures, like with Core i7 or Atom devices. The recent introduction of Intel’s first Xeon system-on-a-chip (SoC) device, the Xeon-D (codenamed “Broadwell DE”), dramatically changes the backdrop range of options for designers of small-form-factor mission computers. The Xeon-D not only provides more cores and threads per CPU (up to 16 cores/32 threads), but also adds a significantly greater number of PCIe lanes than available with Core/Atom devices (32 PCIe lanes for Xeon-D, compared to 16 lanes for Core i7 or six lanes max for Atom).

1. Low-SWaP Mini-PCIe (mPCIe) modules (59.6 × 50.95 mm), such as these MIL-STD-1553 and ARINC429 I/O cards, are becoming increasingly popular in compact embedded systems.

The wealth of PCIe interfaces built into the Xeon-D architecture is ushering in a new era of server-class small-form-factor computing. Beyond the increased throughput, designers are also armed with a greater number of high-speed interface channels that can be routed to more devices. This makes it possible, in many cases, to leverage low-SWaP mini-PCIe (mPCIe) modules (59.6 × 50.95 mm), which are becoming increasingly popular in compact embedded systems (Fig. 1).

The Xeon SoC’s combination of extended operating temperature range (−40 to +85°C, up to 12 cores), low power consumption (45-W TDP), high-core/thread count (12C/24T for extended temp), and numerous PCIe interfaces has made it easier to tailor extremely SWaP-optimized systems. As a result, server-class processing architectures are able to be brought into industrial temperature-deployed applications to satisfy unique vehicle or aircraft interface requirements.

The Xeon in Action

To illustrate the point, using the Xeon-D SoC processor, a hybrid-architecture small-form-factor system can be built using a COM-Express CPU module, mix of mPCIe I/O cards, M.2/mSATA SSDs, and an XMC mezzanine card. This configuration delivers the same amount of PCIe expansion I/O that previously would have required a 50% larger chassis.

For example, with a height of less than 2U (2.3 in./8.13 cm), Curtiss-Wright’s recently introduced Parvus DuraCOR XD1500 rugged mission computer measures just 6.75 in. (17.15 cm) square and deep (Fig. 2). Until the availability of the Xeon-D SoC, a chassis of this size would typically have been limited to a single-board computer (SBC) and potentially two or three mPCIe cards for its add-on I/O.

Given that same chassis envelope, thanks to the Xeon-D’s amount of PCIe interfaces, system designers can double the amount of mPCIe slots while also adding support for an XMC co-processor or another I/O module. This expands the available number of add-on cards that can be integrated into the system from two or three to five or six. Thus, much more functionality (such as MIL-STD-1553, ARINC 429, CANbus, etc.,) can now be integrated into a very small space at a fraction of the cost of larger traditional architectures—without significantly increasing the size or weight of the chassis. On top of that, many mPCIe cards are designed to support industrial temperature ranges and the extreme shock and vibration environments typical of a deployed aerospace or military application.

2. Curtiss-Wright’s Parvus DuraCOR XD1500 features a Xeon-D processor that provides support for a large number of USB 3.0/2.0, 10 Gigabit Ethernet (10 GigE), 1 GigE, and serial interfaces. It utilizes the 32 PCIe lanes from the Xeon-D processor on a COM-Express-based form-factor CPU card, with signals brought to a system carrier board sent out to various I/O modules.

Natively, the Xeon-D provides support for a large number of USB 3.0/2.0, 10 Gigabit Ethernet (10 GigE), 1 GigE, and serial interfaces. The DuraCOR XD1500 fully utilizes the 32 PCIe lanes from the Xeon-D processor on a COM-Express-based form-factor CPU card, with signals brought to a system carrier board sent out to various I/O modules.

The PCIe lanes are divided up for various purposes and interface with a PCIe Switch for flexibility. Such an architecture enables the system to support a high-speed x8 or x16 XMC site while providing multiple x4 PCIe interfaces to Non-Volatile Memory Express (NVMe) storage devices (M.2 and U.2 form factor) and up to 5 mPCIe x1 lanes. These mPCIe slots support low-/moderate-speed interfaces like those used in avionics, vetronics, and networking, as well as other specialized interfaces supported by the mPCIe form factor. The system’s carrier board XMC site can be used to add high-speed graphics or a co-processor, such as an FPGA, GPGPU, or DSP. The mezzanine site can alternatively be used to provide extra 10 GigE NIC ports or other XMC I/O functionality.

The Progression of mPCIe

Previous generations of small-form-factor mission computers from Curtiss-Wright, constrained by the fewer PCIe interfaces supported by Core i7 processors, featured the combination of mPCIe slots and a PCIe104 card expansion bus. A limiting factor relative to high-speed system I/O flexibility for these earlier designs was the relatively small number and type of x8/x16 PCIe104 form-factor modules available in the market. In comparison, the ecosystem of XMC modules is much broader. It also includes a wider range of functionalities, including I/O, graphics, and co-processing cards.

Certain advantages come by way of mPCIe cards, too. They’re very small and cost-effective, each about the size of a business card, with prices typically ranging from $100 up to a couple thousand depending on functionality. These lightweight cards, measured in grams, also have the benefit of being low power and relatively easy to integrate.

Though mPCIe modules first emerged in laptop applications, where they were used to add Ethernet NICs or Wi-Fi modems, their utility has recently expanded. These tiny modules now support a much wider range of functions, such as vehicle or avionics databus controllers, video-frame grabbers, serial interfaces, digital and analog I/O modules, etc.

In the quest to deliver more processing power for embedded applications, without saddling their chassis with unwieldy size or weight, the recent advent of Intel’s Xeon-D SoC opens up new avenues for designers of small-form-factor mission computers. With its greater complement of PCIe interfaces, the Xeon-D SoC enables system architects to take full advantage of the device’s server-class performance while leveraging open standard I/O add-on modules, such as mPCIe and XMC, to expand functionality without increasing SWaP burden.

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