Standard Network Interfaces, Heterogeneous Architecture, and COTS Solutions: Recent Trends in Signal Processing
Published in Military Embedded Systems
As the amount of signal-processing data used in defense applications continues to grow, the challenge for system architects becomes less about hardware design and more about what to do with all that data, and how. Because commercial off-the-shelf (COTS) solutions can now be used to move the data, the system designer can better focus on what they are going to do with that data and concentrate on solving their higher-level problems.
One of the most impactful trends in ISR/EW [intelligence, surveillance, and reconnaissance/electronic warfare] signal processing technology that’s emerged in recent years has been the move toward low-latency open standard network interfaces and their replacement of legacy analog interfaces and some proprietary interfaces. This trend has great significance because the more that signal processing takes advantage of network-based packetized Ethernet-style interfaces, the more modern the overall system architecture can become.
For signal processing applications, the goal is to move incoming analog data from the sensor element(s) to the processing elements as quickly as possible so that the data can be worked on as close to real-time with the lowest latency possible. By rapidly getting that incoming sensor data onto an open standards-based network, the user can powerfully leverage today’s modern high-speed networking standards, whether optical or copper, to move or record it. On the processing side, the use of standard network interfaces liberates the system designer from spending time considering which parts of the system require what different types of interfaces. Until recently, signal processing application designers had to deal with a plethora of interface types. Today, it’s now possible and practical to reduce the number of different interface “flavors” down to a mere handful. That makes it much easier to leverage sophisticated, proven technologies from adjacent markets that also use those standard network interfaces, such as the high-speed data fabrics used in data and financial trading centers.
Different types of silicon bring various strengths
Another major trend in ISR/EW signal processing is the growth of heterogeneous processing. Designers now better understand how different types of silicon – for example, a CPU, FPGA, or GPU – each brings different strengths to signal processing applications. Each type of device brings its own unique strengths and weaknesses. Heterogeneous devices can be clustered together and communicate via modern standard interconnects, such as network interfaces or PCI Express (PCIe) based interfaces, for example, making it easier to mix, match, and balance the signal processing system architecture; or to make the system more extensible, based on the application’s own unique design requirements. In the past, without the use of open standard network interfaces, the signal processing system designer was often forced into a corner, saddled with a system architecture that compromised performance and flexibility because of the need to deal with a variety of arcane interfaces.
Today, thanks to the combination of heterogeneous system architectures and low-latency open standard network interfaces, signal processing system integrators are also better able to develop commercial off-the-shelf (COTS) solutions that enable unique ways of computing. Previously, signal processing customers, not unreasonably, assumed that complex processing requirements would demand a fully custom design approach, often a costly one-off, built only to address a specific task and interfaces at hand. Today, complex signal processing systems can be quickly and cost-effectively addressed with off-the-shelf VITA standard-based hardware. Combining standard network interfaces and heterogeneous compute architectures makes it easier for the system designer to select the right sort of processing technology (while still standards-based), optimized for their particular application and all communicating in an open standard way, to apply new exotic types of algorithms – such as machine learning – to the incoming signals.
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Business Unit Director and Technical Fellow
David Jedynak is Business Unit Director for Curtiss-Wright’s Salt Lake City facility, home of the Parvus small form factor network and computing products. David is also a Curtiss-Wright Technical Fellow. Previously, he served as Chief Technology Officer for Curtiss-Wright Defense Solutions for many years, and continues to provide technology leadership for the group. David joined Curtiss-Wright in 2008, and has focused his expertise in network-centric systems, COTS solutions and Assured Position, Navigation and Timing. He actively drives and supports the adoption of modular open standard approach (MOSA) architectures for the defense industry to accelerate technology deployment. Prior to joining Curtiss-Wright, David worked in both the automotive electronics and film industries on the forefront of industry-wide migrations to cutting-edge open standard digital architectures. He holds a BS Electrical Engineering from UCLA, as well as a Certificate in Astronautical Engineering and a Certificate in Project Management, both also from UCLA.
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