Xeon D and 3U VPX Combine for Cognitive EW
The Role of FPGAs in Cognitive EW
Intel's new Xeon D system-on-chip (SoC) is making large numbers of x86 processing cores readily available for embedded defense applications. With an architecture designed to support math-intensive processing and very-high-bandwidth data transfers, the Xeon D enables advanced cognitive electronic warfare (EW) applications to operate in small size, weight, and power (SWaP)-constrained platforms.
Unlike conventional radar systems, new software-defined digitally programmable radars are able to generate previously unencountered waveforms that do not match known waveforms and pulse trains already on an EW system’s pulse descriptor word (PDW) list. The PDW typically contains all the collected data for a specific pulse, including time of arrival (TOA); angle; pulse width, power, and frequency (superhet); or frequency band. In order to defeat never-before-seen waveforms, system designers are developing a new generation of cognitive EW systems that are able to quickly adapt to changes in the radio frequency (RF) environment and almost instantly make decisions about how to respond to unfamiliar threats.
These cognitive EW systems are well served by the recent introduction of new multicore Intel Xeon processor D (Xeon D) devices that deliver the greater thermal range performance required by SWaP-constrained EW pod environments. Cognitive EW systems built with these new devices promise to provide an alternative to today’s EW systems, which are typically implemented with field-programmable gate array (FPGA)-based system-level architectures. While FPGA-centric EW systems that implement digital radio frequency memory (DRFM) and other EW techniques in firmware via VHDL and Verilog are sufficient for intercepting and prosecuting known waveforms and pulse trains on the PDW list, they lack the dynamic flexibility needed to counter new waveforms generated on the fly by sophisticated adversaries using digitally programmable radar.
The Role of FPGAs in Cognitive EW
That’s not to say that FPGAs don’t play an important role in these new cognitive EW systems. Unlike general-purpose processors, FPGAs are very good at sophisticated highly parallelized, high-throughput DRFM techniques such as range gate pull-off. FPGAs, however, are not very good at making decisions and dynamically changing their own architecture, which is key to cognitive EW. One approach for implementing deployable embedded cognitive EW is to couple a cluster of general-purpose Intel x86 cores – such as the eight, 12, or 16 cores available on a Xeon D – with large FPGAs. In this type of heterogeneous system architecture, the FPGA provides high-speed parallelization while the Xeon D provides the required real-time supercomputer-class analytic and metadata processing. The decision-making speed of the system’s Xeon D cores and the processing performance of the FPGA work in concert to enable the system to respond to unknown waveforms by synthesizing a mix of responses to quickly create the best defense against the new threat. This response may include the partial or complete reconfiguration of the FPGA, depending on the findings of the Xeon D. The extremely low-latency decision-making capability of the x86 cores actually enables the cognitive EW system to select the proper set or mix of signal-manipulation techniques to adapt to the threat while in-theater.
Intel Processing Solutions
Today’s embedded, aerospace and defense industries rely heavily on modern commercial technology to meet the demanding power, size, and performance requirements of today’s mission-critical systems. Intel’s tick-tock technology cadence, which alternates microarchitecture advancements with power-saving die geometry shrinkage, has produced continuous performance improvements with reliable, scalable processing options available to suppliers of SBCs and DSP engines for use in embedded control, processing, and compute-intensive applications.