Accelerating Radar Processing with FPGAs and C-to-Gates Methodology
High-performance, scalability, and capacity are key factors in designing COTS embedded system as algorithms and sensors are continually improving. With Radar and Electronic Warfare (EW) systems specifically, complex processing has to be done in real time to keep up with incoming data. Because of this, designers turn to FPGAs for their superior processing speed and parallel processing capability.
Radar and EW systems have an ever-increasing need for compute capacity, and incorporating FPGAs into the processing chain provides a flexible alternative to general purpose processors. FPGAs contain hundreds of thousands and even millions of configurable logic blocks as well as thousands of DSP cores which can be used for implementing Radar or EW functions. If DSP algorithms are written in a way to take advantage of these massive resources, FPGAs can significantly outperform general purpose processors running the same code. Combining the latest generation FPGA modules with multiple FPGAs on them provides a powerful platform able to process 10s of TeraOps per second. These modules also require communication at high data rates but modern backplanes are more than capable of this task.
Using multiple FPGAs can increase capacity and real-time processing speeds, but designing FPGAs quickly becomes expensive and time consuming. Radar and EW developers require the latest generation FPGAs, but new FPGA generations emerge every 18-24 months with twice the capacity as the last. By combining multiple FPGAs with the use of a C-to-Gates design flow, you can reduce the heavy investment of a long design process and still meet demanding processing needs. Designing FPGAs with high-level synthesis is a modern approach to help speed the process and quickly reap the benefits of multiple high performance FPGAs.
Download the white paper on Accelerating Synthetic Aperture Radar Processing to learn more about:
- FPGA based COTS modules
- Rapid FPGA design using C-to-gate synthesis
- Acceleration of DARPA Synthetic Aperture Radar Benchmark using FPGAs
- Multi-FPGA + CPU System Design