Combatting Sample Clock Jitter with Signal to Noise Ratio in a New World of High Resolution Data Converters

clock jitter
clock jitter
Blog
December 16, 2016

Combatting Sample Clock Jitter with Signal to Noise Ratio in a New World of High Resolution Data Converters

Good quality sample clocks used by Analog to Digital Converters and Digital to Analog Converters are sometimes overlooked. What is meant by a good quality clock anyway?

Some see this as a free running clock that is very stable over time. But what about jitter, the cycle by cycle timing differences that affect real-world systems? Jitter is becoming more of a problem as ever faster and higher resolution data converter devices come onto the market. A given amount of jitter will result in a larger error as an input signal frequency to an analog to digital converter increases. In simple terms, jitter is a noise source that’s becoming increasingly more important to limit.

A significant system performance parameter is Signal to Noise Ratio (SNR). All analog to digital converters will have a signal to noise ratio specification for a given input and sample frequency, creating a budget for how much noise can be tolerated by clock jitter before it affects the Signal to Noise Ratio parameter. It is important to remember there are other noise sources as well, and especially so for wideband applications with more potential sources and the increased resolution of high speed converters.

Jitter isn’t confined to the irregularities in a sample clock, but also includes RF switches, distribution buffers and inside the analog to digital converter itself. The latter, otherwise known as aperture jitter, is due to the cycle-by-cycle sampling instance variations in the sample and hold circuitry.

We won’t dive deep into the math behind jitter nor its definition, as there are many learned discourses available, but it is worth outlining some useful formulas relating to the noise associated with jitter. Since jitter is noise, it can be defined in the same way as any other SNR noise parameter.

Rearranging this, for a given Signal to Noise Ratio we can show the amount of jitter budget before signal to noise ratio is affected by jitter. Jitter is measured as an RMS sum of time, usually in picoseconds or femtoseconds.

For a typical multi-Gsps analog to digital converter, a jitter budget could be around 250fs, a distribution buffer could be 15-75fs, and aperture jitter may be around 100fs. All these sources can add up, and ultimately all clocks will have some level of jitter.

The key is being aware of it and managing it through design and component selection. There are many other forms of noise including cross-talk, ADC spurs, front end amplifiers and even mismatched signal traces, but jitter is becoming a more significant contributor and one definitely not to be ignored.