Dissecting All-to-All Architecture: the ultimate COMINT/ELINT signal analysis methodology

Blog
Blog
Blog
February 28, 2017

Dissecting All-to-All Architecture: the ultimate COMINT/ELINT signal analysis methodology

 

 

 

Figure 1: All-to-All Architecture

The figure above represents a conceptual flow diagram of the “All-to-All” architecture presented in the Curtiss-Wright Defense Solutions white paper “Dominating the Electromagnetic Spectrum with the Ultimate in COMINT/ELINT Signal Analysis Methodologies, the All-to-All Architecture.”

In this all-to-all architecture, six high channel count DRS Technologies’ Vesper Radio Frequency (RF) tuners interconnect to six high core count Curtiss-Wright CHAMP-XD Intel Xeon D modules via two high density 40/10 Gigabit Ethernet switches all in a single OpenVPX chassis. Sensors, such as the Vesper multichannel RF tuners/exciters, inject their IF/baseband results over a high rate, low latency multicast data fabric, which can then in turn forward the data from any RF channel to any processor core. Alternatively, and in unison, data can be routed to recorders for post mission analysis.

Leveraging elite tools from the supercomputing world, high performance embedded computing applications can benefit in ways we’ve never seen before. Curtiss-Wright’s OpenHPEC Accelerator Suite enables the coordination and arbitration of complex data flow paradigms and optimizing standard middleware by profiling and benchmarking using the latest in visualization techniques.

With this unparalleled flexibility comes the potential for great complexity in terms of managing massive Ethernet traffic and packet routing so that high throughput, low latency, and efficient arbitration are maintained. This incredibly dynamic Ethernet infrastructure represents a serious amount of software development, integration, and testing.

Here is just a subset of some of the challenges to anticipate:

  • Avoiding dropped packets, not a desirable attribute in SIGINT applications
  • Maintaining low CPU utilization on the Intel Xeon D processors associated with packet transfer via RDMA/RoCE
  • Arbitration of Ethernet traffic due to overlapping multicast and unicast transactions
  • Efficient application of VITA-49 VRT over UDP Ethernet
  • Buffering of massive data streams in Xeon D DDR4 memory

 

Curtiss-Wright Defense Solutions has put its top Application Engineers on the job to solve this high order problem. By providing not just the hardware components, but also the network software infrastructure, our customers can focus on what they do best, the application.