FMC+ - Ready for the Mainstream

April 26, 2016

FMC+ - Ready for the Mainstream

There’s a buzz about the new FMC+ standard which has targeted key new technology standards

What’s not to like about the emerging field-programmable gate array (FPGA) mezzanine standard, FMC+ from the VITA standards committee? FMC+ addresses the need for an increased number of Multi-Gigabit Transceivers (MGTs) while retaining all the goodness and backwards compatibility of the industry standard FMC format. The benefit from having all of the additional MGTs increased from 10 to 24 with a further option for up to 32 is to allow developers to exploit devices using JESD204B, high-speed/high-density fiber-optics or even newer memory technologies like Hybrid Memory Cube (HMC). 

Parallel to JESD204B Image

Driven by the telecommunications industry’s need for smaller, higher performance and lower cost infrastructure, MGT interconnect allows for smaller components without sacrificing performance. The only drawback is perhaps an increase in I/O latency, although still small, for some very sensitive applications such as Electronic Warfare (EW). 

The JESD204 (currently at the B revision) standard has been around for a number of years and has now become the de facto interface standard of choice for high-speed devices. Many of the large I/O chip vendors for high-speed analog to digital converter and digital to analog converter devices have now switched to JESD204B with parallel interfaces alternatives starting to be phased out, though there are still some specialist vendors. Analog to digital converter and digital to analog converter devices are now available with sample rates in the mid-GSPS range and within a year likely to break through the 10GSPS barrier. From a practical perspective, parallel interfaces for such fast I/O components would require so many I/O pins and large packages that even the largest of the latest generation of FPGAs could be overwhelmed. This means fast serial connectivity is the future for wide bandwidth I/O. In the world of high-speed I/O, small is beautiful and FMC+ balances I/O connectivity and device package size for powerful and flexible solutions. 

Formally known as VITA 57.4, and soon to go through the ANSI adoption process, FMC+ is gaining a lot of momentum and the first products have already been announced such as Xilinx’s new FPGA evaluation cards and more product releases are expected soon. There is a buzz in the industry. To find out more on the FMC+ (VITA 57.4) specification, take a look at an article in Xilinx’s latest edition of Xcell


FPGA Mezzanine Card (FMC) Standard

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