Getting Ready for an I/O Leap: FMC to FMC+
An evolving standard will take advantage of serially connected FPGAs and I/O devices.
The current FMC specification is very capable, but needs a boost to cope with emerging technology. New I/O devices, especially high-performance ADCs and DACs are challenging FPGA throughput. They offer great size and power advantages but rely on high-speed serial interfaces, a challenge for the current FMC standard, which has most of its pins allocated to parallel I/O signals.
FPGA Mezzanine Cards (FMCs), under the banner of VITA 57, exist to provide I/O directly to FPGAs – high bandwidth I/O that can keep increasingly powerful FPGAs fed with data, so their processing operations proceed without waiting. The FMC standard has done that job well, becoming the open standard mezzanine of choice for analog I/O. Now it must adapt.
FMC to FMC+
Specifically, the FMC specification must evolve to take advantage of serially connected FPGAs and I/O devices. New ADCs and DACs are rapidly moving to ever-higher resolutions, usually using the space-efficient JESD204B serial interface. These fast moving advances are fueled by the telecommunications industry, but the embedded defense community can take advantage of them to meet SWaP-C requirements.
The size advantage of the smaller JESD204B devices means that more of them can be fitted on an FMC footprint. More channels, all with more bandwidth, for each mezzanine card. However, to take full advantage of the new devices, FMCs need more high-speed serial connections.
An effort to define suitable FMC enhancements is now underway within the VITA 57.4 working group, under the preliminary name 'FMC+'. It aims to provide full backward compatibility while delivering a huge leap in I/O throughput.
It should be noted that the FMC+/VITA 57.4 is being still developed and could change, but VITA recognizes the need for an enhanced specification. To get insight into the details, read the white paper.