This Matters: Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range (SFDR) is a critical parameter for assessing the ability of a particular ADC or DAC to process or generate an analog signal. For applications processing sensor data or generating specific waveforms, SFDR represents the smallest signal that can be distinguished from any other artifacts that are generated as part of the processing. The larger the magnitude of SFDR, the better.
Measured in the frequency domain, SFDR is defined as the ratio between (1) the strength of the signal of interest and (2) the strongest spurious (artificial) signal in the background. It represents the usable dynamic range before a spurious signal interferes with or distorts the signal under test.
The spurious signals can be noise, but not always. They can also be caused by:
- harmonics of the primary signal due to nonlinearities of the ADC/DAC converter
- harmonics of the sampling frequency due to clock coupling
- artifacts of the method used to capture/generate the signal (i.e. interleaving or interpolation)
- clock purity
Depending on the application, the next strongest (spurious) signal may be outside of the signal range of interest; in this case, SFDR may not be critical. Knowing the location of spurious signals is important in making a determination as to whether or not they are relevant.
Because SFDR is a ratio it is measured in decibels (dB). SFDR is dependent on bit resolution and can range from approximately -40 dB (1/100th) for ADC/DACs under 8 bits, to -60 dB (1/1000th) for mid-range ADC/DACs to less than -90dB for 16 bit ADC/DACs. SFDR also is typically better for lower frequencies than higher frequencies.
Real World SFDR
Most commonly SFDR is measured by comparing the peak of the signal of interest to the next largest peak in the spectrum. The result is measured in dBc (where c stands for the carrier).
In some cases, SFDR compares the full scale of what the ADC can measure against the largest non-signal peak. This is measured in dBFS and results in a higher value.
The graph below is from the CHAMP-WB-DRFM 6U VPX DRFM Processor Card Set sampling a 3.2 GHz signal at 12 GS/s; it shows how SFDR is measured when looking at a spectrum of a received signal using dBFS. All reported parameters are related to full-scale range of the ADC, even the signal of interest. However, just comparing the signal against the next largest peak results in a delta of ~55 dBc.
Measuring SFDR for the CHAMP-WB-DRFM in dBFS
Finding SFDR Data
Design engineers need to evaluate SFDR values when comparing available ADC/DAC options. Typical SFDR for Curtiss-Wright products can be found in product datasheets, while more detailed information is available upon request. Examples include:
- FMC-516 Quad 250MSPS 16-bit ADC FMC Module
- FMC-518 Quad 500MSPS 14-bit ADC FMC Module
- VPX3-530 3U VPX Xilinx Virtex-7 FPGA ADC/DAC
- CHAMP-WB-DRFM 6U VPX Digital RF Memory Card Set
Senior Product Manager - FPGA
Denis Smetana is Senior Product Manager for FPGA products for Curtiss-Wright Defense Solutions, based out of Ashburn Virginia. He has over 25 years of experience with ASIC and FPGA product development and management in both the telecom and defense industry and over 10 years of experience with COTS FPGA products. He has a BSEE in Electrical Engineering from Virginia Tech.