Understanding FMC interoperability

August 05, 2011 | BY: Steve Edwards

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New generations of FPGAs present developers with a level of processing performance and potential I/O bandwidth that cannot easily be matched by conventional CPU configurations. The FPGA Mezzanine Card (FMC) (ANSI/VITA 57.1) directly addresses the challenges of FPGA I/O by solving the dual problem of how to maximize I/O bandwidth while still being able to change the I/O functionality. FMCs offer an elegant, simple solution because they only host I/O devices, such as ADCs, DACs, or transceivers.

Advantages of FMC
FMC modules have no onboard processors or bus interfaces, such as PCI-X. Instead, FMC modules take advantage of the intrinsic I/O capability of FPGAs to separate the physical I/O functionality on the module from the FPGA board design of the host of the module, while maintaining direct connectivity between the FPGA and the I/O interface. In comparison, PMC/XMC mezzanine modules implement a fairly generic interface, usually using PCI (PMC) or PCI Express (XMC). Their electrical interfaces are well defined so that the host can deal with all hardware in a common manner. For PMC/XMC modules, the main reliance is on the software driver for determining how this interface is controlled on the other side of the PCI or PCI Express interface.

Because the PMC/XMC interface is generic and abstract, there is a good chance that a PMC with, for example, a VxWorks 6.5 driver for a Power Architecture-based host card will work on any VxWorks 6.5 Power Architecture host (with a PMC site) with little or no modification. On the other hand, FMCs are different. FMCs operate at a very low level, and the probability of direct interoperability between host cards with no code changes is low. However, the advantages of FMCs for high- performance applications are considerable: high-bandwidth, low-latency interfaces; lower power; and more I/O real estate.

The FMC specification does not define a generic interface. Instead, it defines a maximum number of FPGA connections. Thus, the FMC's I/O devices are very intimately connected to the host card's FPGA. There are no buses such as PCI to contend with. But this flexibility requires more direct control. The exact FPGA connectivity - for example, which pins are utilized and FPGA type - needs to be considered. All FPGA hosts will be different, even within a family such as a Xilinx Virtex-5 SX95T and a Xilinx Virtex-5 SX240T.

LPC and HPC defined
The FPGA tools environment is also critical. When a single vendor supplies both the host processor and the FMC card, it will be easier to supply software/HDL optimized for the low-level connectivity of the host and its environment. Sometimes, though, it is preferable to use an FMC and a host card from different vendors. FMC allows for two sizes of connector, Low Pin Count (LPC) and High Pin Count (HPC), each offering different (maximum) levels of connectivity, analogous to how some PMC boards have a 32-bit interface while others have a 64-bit interface by using an additional connector. The LPC offers up to 68 differential pairs while HPC offers up to 80 differential pairs. Curtiss-Wright Controls Embedded Computing's (CWCEC's) FMC-516 (Figure 1) is a quad-channel, 250 MSps, 16-bit analog input card that enables I/O devices to be directly coupled to a host FPGA. By providing direct ADC connection to the host FPGA, this card ensures maximum throughput and enables multiple channels and boards to be synchronized.

FMCs with HPC connectors cannot usually be used on LPC FMC hosts. The LPC is a subset of HPC and so some combinations yield reduced functionality. But HPC FMCs will typically not work on LPC host boards. Also, not all HPC FMCs can be used on every HPC FMC host. And there are FMCs with more connectivity requirements than some hosts can provide, even if the host is identified as an "HPC FMC"host. As FMCs continue to increase in popularity, thanks to their high-bandwidth, low-latency interfaces, lower power, and increased I/O real estate, it is important to be familiar with the differences between different classes of FMC cards so that interoperability can be maximized and the benefits of these flexible, compact I/O cards are optimized.

Author’s Biography

Steve Edwards

Director, Secure Embedded Solutions & Technical Fellow

Steve has over 25 years of experience in the embedded system industry. He managed and co-designed Curtiss-Wright’s first rugged multiprocessor and FPGA products and was involved in the architecture, management and evangelization of the industry’s first VPX products. Steve has Chaired the VITA 65 working group and currently leads Defense Solutions’ strategic initiative in Anti-Tamper and Cybersecurity. Steve has a Bachelor of Science in Electrical Engineering from Rutgers University.

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