The Clock Starts and Stops Here
May 11, 2018 | BY: Jeremy Banks
Solving problems of phase accurate synchronization can be challenging. Particularly if it includes trying to achieve synchronization of analog signals through multiple analog to digital converters at multi-GHz rates on a single card, or synchronization between multi-boards or systems over wide temperature ranges.
The case for phase accurate synchronization proved to be a conundrum for a group of systems designers. To achieve optimal synchronization, eight of Curtiss-Wright’s VPX3-530 transceivers; each with four 2 Gsps data converters requiring cycle accurate synchronization was put to the test. The VPX3-530 was designed for synchronization; however, each needed an external master reference clock to take on the challenge. The VPX3-530 meticulously exploits the XCLK1’s clock stopping mechanism to stop the sample clocks to the RF ADCs, halting data conversions under the control of the card’s FPGA. Curtiss-Wright’s XCLK1 Multi-Clock Generators were selected to provide RF clock distribution for up to 12 outputs to achieve this goal.
Synchronization starts with the perfect board.
The VPX3-530 uniquely combines multiple channel high-speed ADCs and DACs with a latest generation user programmable Xilinx Virtex-7 FPGA. It features:
- Dual 4 Gsps 12-bit or Quad 2 Gsps 12-bit analog inputs
- Dual 5.6 Gsps 14-bit DAC update rate (maximum 2.8 Gsps data rate)
- Multi-board, multi-channel synchronization
- Xilinx user programmable Virtex-7 VX690T FPGA
- Up to 8 Gbytes DDR3L SDRAM (64-bit data paths)
- 3U OpenVPX compliant
- Onboard power and temperature measurement
- VxWorks and Linux host support
- Air- and Conduction-cooled variants
The XCLK1 Multi-Channel Clock Generator offers
- Ultra Low Jitter Multi-Channel Clock Generator
- Up to six phase matched RF outputs
- Selectable internal or external clock reference sources
- XMC/PMC format (power only)
- It also includes air-cooled and rugged build options
The use of the VPX3-530 along with the XCLK1 offered a masterful solution to a complex problem. The result, a robust system level solution with consistent power up and stable synchronization. Moreover, with the ease of IP integration the systems designers are now able to focus their efforts on the application itself, free of the complexities associated with achieving multi-board synchronization.