Combatting Sample Clock Jitter with Signal to Noise Ratio in a New World of High Resolution Data Converters

December 16, 2016 | BY: Jeremy Banks

Good quality sample clocks used by ADCs and DACs are sometimes overlooked. What is meant by a good quality clock anyway?

Some see this as a free running clock that is very stable over time. But what about jitter, the cycle by cycle timing differences that affect real-world systems? Jitter is becoming more of a problem as ever faster and higher resolution data converter devices come onto the market. A given amount of jitter will result in a larger error as an input signal frequency to an ADC increases. In simple terms, jitter is a noise source that’s becoming increasingly more important to limit.

A significant system performance parameter is Signal to Noise Ratio (SNR). All ADCs will have an SNR specification for a given input and sample frequency, creating a budget for how much noise can be tolerated by clock jitter before it affects the Signal to Noise Ratio parameter. It is important to remember there are other noise sources as well, and especially so for wideband applications with more potential sources and the increased resolution of high speed converters.

Jitter isn’t confined to the irregularities in a sample clock, but also includes RF switches, distribution buffers and inside the ADC itself. The latter, otherwise known as aperture jitter, is due to the cycle-by-cycle sampling instance variations in the sample and hold circuitry.

We won’t dive deep into the math behind jitter nor its definition, as there are many learned discourses available, but it is worth outlining some useful formulas relating to the noise associated with jitter. Since jitter is noise, it can be defined in the same way as any other SNR noise parameter by using:

Rearranging this, for a given Signal to Noise Ratio we can show the amount of jitter budget before SNR is affected by jitter:

Jitter is measured as an RMS sum of time, usually in picoseconds or femtoseconds. The various sources of jitter should therefore be added together as set out below:

For a typical multi-Gsps ADC, a jitter budget could be around 250fs, a distribution buffer could be 15-75fs, and aperture jitter may be around 100fs. All these sources can add up, and ultimately all clocks will have some level of jitter.

The key is being aware of it and managing it through design and component selection. There are many other forms of noise including cross-talk, ADC spurs, front end amplifiers and even mismatched signal traces, but jitter is becoming a more significant contributor and one definitely not to be ignored.

Author’s Biography

Jeremy Banks

Product Marketing Manager, ISR Solutions

Jeremy Banks is a Product Marketing Manager for Sensor and I/O Processing in the ISR group at Curtiss-Wright. He has been involved in the defence embedded computing industry for over 25 years holding positions in engineering design, marketing and product management in DSP, Multi-Processing, RF IO, SBCs, FPGAs and System solutions. Jeremy is a graduate of the University of Surrey in Electronic and Electrical engineering.

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