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FPGA Processing: Challenges and Considerations

December 15, 2014 | BY: Denis Smetana, Jeremy Banks

Looking at 3U VPX, 6U VPX/VXS and PMC/XMC form factors

As FPGAs (Field Programmable Gate Arrays) provide immense processing capability, their size can challenge developers when it comes to fitting all necessary resources for a system within the standard board factors most common in the defense market, such as 3U VPX and 6U VPX/VXS, and mezzanine cards, such as PMC/XMC. However, the march towards higher processing and I/O density means that some solutions that could only be achieved using 6U solutions in the past can now be achieved in 3U - and multi-rack 6U solutions be achieved in a single rack. Along with the cost and size savings, there are challenges and considerations too.

Which form factors you choose depends on the I/O and processing capability your application requires, as well as the available space and shape for the target application.

  • PMC/XMC mezzanine cards often are the go-to solution for adding required functionality without taking valuable space on the host board. They also reduce weight - a critical consideration for SWaP-constrained platforms such as UAVs.

    Typically, mezzanine cards accommodate a "medium"sized FPGA and provide significant functionality in terms of density per square inch. A drawback of PMC or XMC cards, however, is that most of their components face the host card, exposing them to heat from the host, while the host can also be impacted from heat generated by the mezzanine. Significant cooling technology is required for a mezzanine card that exceeds 7-15W of power. FPGA-based PMC/XMC can dissipate 15-25W power and therefore require careful consideration for not only the mezzanine, but the host too for an effective implementation - especially with high temperature rugged environments.
  • 3U VPX cards provide about 50 percent more usable space than PMC/XMC mezzanine cards, and are suitable for accommodating a larger FPGA, and in some cases an additional smaller FPGA device along with the rest of the I/O. They offer a power budget of up to 100W using standard cooling techniques, and some provide space for a mezzanine card.

    With a 3U card, heat is less of a factor. Unlike on a mezzanine card, components face out, allowing heat to convect for an air-cooled solution or provide a low thermal impedance because of more available space for a larger (thicker) heatframe. A typical 3U system is composed of four to six card slots.

    Despite a common misconception, 3U cards offer less than half the usable real estate available in the 6U form factor because there is fixed overhead which is the same for both 3U and 6U card sets. This is especially true when conduction cooling is used due to bulky wedgelocks along the side of each card. This means a 6U card offers more than twice the functionality of a 3U card.
  • While larger, heavier and more costly than 3U alternatives, 6U FPGA processor cards can be more efficient, in terms of cost per data processing channel, when more than 1 FPGA is required in the system.

    A 6U card can accommodate three or four medium to large FPGAs with total power dissipation often exceeding 150W, and they have room for 10 to 20 card slots. Some designers, depending on their application needs, opt to trade out an FPGA for additional IO, in some cases with flexible mezzanines, to support optimal IO latency.

    The limiting factor for a 6U card, for conduction-cooled solutions, is that they have longer thermal paths than a 3U card. FPGAs closer to the card edge can be cooled easier than ones located in the middle of the card.

Lastly the system level interconnect needs to be analyzed in terms of number of channels, interconnect bandwidth and Processor-FPGA interface protocols. Sometimes, the number of channels that need to be supported are limited by the form-factor rather than the FPGA resources depending on how much FPGA processing is required per channel. Evaluating the inter-card bandwidth that is required or the bandwidth needed between the processor and the FPGA may lend itself better to one solution or the other. PCIe is very common for XMCs and 3U VPX, while SRIO, 40GbE, or Infiniband are more likely to be found in 6U platforms only. Although there are exceptions as there are some SRIO based XMCs and Gen3 PCIe is quite common on newer Gen3 products.

Chassis backplane configurations also play into this and it is important to understand OpenVPX backplane profiles to understand what interconnects are readily available in off-the-shelf backplanes and which may require more customization. Larger cards have more backplane I/O to facilitate more backplane connections. But with both 3U and 6U as you add more cards you either need to incorporate switches to provide flexible interconnect options or you need to insure there is sufficient backplane I/O for dedicated point-to-point routes.

When defining an FPGA based solution, here are some considerations based on the card format

  • How many FPGA resources is required? Can the resources be accommodated in a single or multiple devices?
  • Is a "medium"sized FPGA sufficient? If so, latest generation FPGAs offer solutions which can now be achieved on a simple mezzanine.
  • How much power is likely to be dissipated? If space isn't an issue, a larger format card may be better, even if there is a product available using a small card format, especially if the overall temperature environment is severe.
  • What is the size and shape of the area that will house the system? The larger the format the card, the more efficient it can be - but there might be a trade-off between size, weight and cooling capability.
  • What are the I/O constraints relative to the FPGA and system level interconnect? This includes number of channels per FPGA, and inter-card bandwidth requirements.

FPGA Density per card format

Format FPGA Resource Card Power Typical System Size
PMC/XMC 1x Medium 10-25W N/A
3U VPX 1x Large + 1x Small 60-100W+ 4-5 cards
6U VPX 3-4x Medium/Large 150W+ 10-20 cards

 

For help in finding the best solution for the required performance of your application, contact the Curtiss-Wright Defense Solutions team.

 

Author’s Biography

Denis Smetana

Senior Product Manager - FPGA

Denis Smetana is Senior Product Manager for FPGA products for Curtiss-Wright Defense Solutions, based out of Ashburn Virginia. He has over 25 years of experience with ASIC and FPGA product development and management in both the telecom and defense industry and over 10 years of experience with COTS FPGA products. He has a BSEE in Electrical Engineering from Virginia Tech.

Author’s Biography

Jeremy Banks

Product Marketing Manager, ISR Solutions

Jeremy Banks is a Product Marketing Manager for Sensor and I/O Processing in the ISR group at Curtiss-Wright. He has been involved in the defence embedded computing industry for over 25 years holding positions in engineering design, marketing and product management in DSP, Multi-Processing, RF IO, SBCs, FPGAs and System solutions. Jeremy is a graduate of the University of Surrey in Electronic and Electrical engineering.

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