How Intel Xeon D can boost compute power AND solve sensor fusion challenges
April 11, 2017 | BY: Marc CoutureDownload PDF
Without a doubt, the Intel Xeon D represents the most significant device for the Defense Industry in a while. This isn’t just because it is a true System-On-Chip in an extended temp BGA package, but because it is a whole family of Xeon D chip SKUs with a common footprint. Board developers such as Curtiss-Wright can produce a single PCB that can then hold any one of the Xeon D SKUs, enabling the application developer to choose the best Xeon D for the job. The trade space at this silicon SKU level includes number of cores vs. TDP vs. clock frequency vs. standard or extended temperature.
A different trade can be made at the board level in terms of architectural optimizations. As per Figures 1a and 1b, Curtiss-Wright is currently producing two 6U OpenVPX modules based on the Intel Xeon D, the CHAMP-XD2 and the CHAMP-XD2M. The XD2 contains two Xeon D devices with up to 32 GBytes of DDR4-2133 each, providing up to 32 cores on a single module in total. In contrast, the XD2M contains a single Xeon D with up to 16 cores, however 128 GBytes is available to the processor. Another way to look at it is the CHAMP-XD2 provides for 2 GBytes per Xeon D core as opposed to the CHAMP-XD2M, which provides for 8 GBytes per core, keeping in mind that the XD2M has half the core count as the XD2 per VPX board slot.
|Figure 1a: CHAMP-XD2 for more COMPUTE||Figure 1b: CHAMP-XD2M for more MEMORY|
The needs of the sensor processing application should dictate which board architecture makes the most sense. If the application is compute bound with VPX slot-count constraints, then the CHAMP-XD2 is the clear winner. In other words, if you need as many Xeon D cores as possible per a given subset of board slots, the CHAMP-XD2 is the way to go. Other applications may however be memory bound, in which case throwing more compute cores at the problem does not provide the solution. High data-rate sensor ingest applications (e.g. Sensor Fusion) and mobile server (e.g. Hypervisor VMs) may favor maximum memory capacity, in which case the CHAMP-XD2M is the clear choice as four times the amount of memory capacity is available for data ingest, cueing, etc. Some payloads may have multiple sensor processing stages and/or functions, in which case both modules may need to be present within the same OpenVPX chassis. The combination of Intel Xeon D chips and Curtiss-Wright CHAMP-XD boards represents the ultimate in flexibility and optimized performance for the application developer.
Download our Intel Xeon D: A Significant Leap Forward White Paper to read more about:
- Intel Xeon D
- Using a common technology for multiple applications
- Maximizing compute power
- Overcoming sensor fusion challenges
- Tackling the mobile server