The Evolution of Analog to Digital and Digital to Analog Technology
March 22, 2017 | BY: Jeremy Banks
Like any progressing technology, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) technology has been subject to ever-higher performance provided by smarter designs and shrinking device geometries for decades. However over recent years, ADC and DAC technology has been marked by not only performance improvements including speed, resolution, bandwidth, channel density, and lower power, but higher levels of functionality and newer platforms to support the newer devices. This trend is accelerating to provide some exciting possibilities.
The JESD204B interface has now become the default interface for high-speed analog IO components, though fast devices with parallel IO interfaces are still being developed. High speed analog IO devices may use around 96 digital IO pins (48 LVDS pairs for a 12b device) for each channel due to the multiplexed data busses required to interface to FPGAs. The key benefit of JESD204B is the need for fewer IO pins. As a comparison, the 96 pin parallel data bus signals can be compressed into just eight differential pairs – with some devices halving even this if used on the very latest generation of FPGAs. Since the number of pins dominates what the package size needs to be, serially connected ADC or DAC packages have shrunk to around a quarter of the size of their parallel counterparts. To put this into context, high-end parallel ADC and DAC devices have been typically the largest devices on a circuit card, next to the FPGAs. The net saving in space is reasonably significant. Moreover, since the parallel devices consumed so many of the FPGA’s IO pins, only a few could be used with any one FPGA.
JESD204B does have a couple of potential drawbacks. Some applications, such as Electronic Warfare (EW), care about latency. A JESD204B equivalent of the same device with a parallel interface has increased latency by anything up to ten times. However, latency is usually a function of the sample rate (i.e. a fixed pipeline), so the faster the sample rate, the faster data emerges from the pipeline. As the newer devices with faster sample rates come to market, latency for even JESD204B connected parts should reduce. The second drawback for smaller packages with the same analog IO components can mean the package heat density increases. For now this is minor, but for rugged high temperature applications, the design needs to take this into account.
In short, the device size has caused a significant reduction in the component size, offering a very real boost for SWaP sensitive applications. For others, JESD204B parts mean functionality can fit into a given form-factor whereas before it just wasn’t an option.
Driven by JESD204B and other high-speed serial data link requirements in the new FMC+ mezzanine specification controlled under VITA 57.4., FMC+ increases the maximum number of HSS links from 10 to 24 (or 32 with the extension connector). This more than doubles the capability, not to mention the speeds of the individual links. See here for more details behind FMC+.
Multi-Gsps ADC and DACs are firmly into the 3-6 Gsps territory with very good resolution (12b+) and good bandwidth to match. The 10 Gsps boundary should be broken within the next year along with multi-channel 14b+ devices in the mid-Gsps. Today’s ADCs are able to fully digitize parts of the multi-GHz spectrum in first Nyquist sampling including L-band and some S-band frequencies at native 12-bit resolution, and into X-band. At these speeds and resolutions, tuner-less SDRs, RWR and RADARs are becoming a more practical solution.
More integration and enter FPGAs
A key trend seen today is analog IO devices as more than just an analog IO device. It has now become common for the faster ADCs to include DDCs on chip, which can be entirely bypassed if needed. Although basic at first, this component has become quite sophisticated. The net effect is that unwanted data is removed at source, making it less likely to clog up the datalinks or allow some JESD204B designs to reduce fewer datalinks in the first place. Some devices have also started to incorporate more sophisticated analog front ends. These include buffers or even local analog mixers to down convert signals onchip thereby allowing direct connection to the antenna by sucking up much of the external RF components.
Integration can come from multiple directions. Not only are ADCs adding in new functionality, but ADCs themselves are now being incorporated into FPGAs directly.
Xilinx recently announced their RFSoC family; ADCs have been integrated with FPGAs for quite some time, but not on this level of sophistication and speed Xilinx is now providing. The switch to serial IO for fast ADCs is no longer necessary if they are part of the FPGA themselves since they do not need to accept the compromise of latency to save package size and the number of signals needed. Having ADCs and DACs on the FPGA is a powerful and likely disruptive evolution of high-speed analog IO solutions. The next generation of these parts will also include processor for true SoCs, but analog and digital. The first parts of this generation will have relatively small FPGA resources, but the analog IO will be blisteringly quick and aimed squarely at telecommunications applications.
With that said, architectures for other applications are not so dissimilar if high-end processing is not needed. For the highest performance applications, the flexibility and scalability of discrete high-end FPGAs interfacing to a large number of high-end ADCs and DACs will be the mainstay for quite a while. However, the definition of what is an ADC, what is an FPGA, or what is a CPU is likely to be blurred in the future as each function breaks out of its pigeonhole in such a way as to offer real high-performance solutions in very small footprints. From systems based on a collection of boards, to a collection of devices to all being on a single chip, it is all starting to get interesting.