The CHAMP-XD1S is no longer recommended for production programs. For the latest in 3U VPX DSP modules, please view the CHAMP-XD3.
The CHAMP-XD3 3U VPX Intel Xeon D DSP module provides the same enhanced Trusted Computing features as the CHAMP-XD1S, and was developed in alignment with the SOSA Technical Standard.
- Intel Xeon D 12-Core (576 @ 1.5 GHz)
- Extended operating temperature Intel eTEMP SKUs
- PCH integrated in Xeon D SoC
- Xilinx MPSoC FPGA with embedded quad A53 processor and 4 GB of DDR4 memory for enhanced security or coprocessor functionality
- Microchip SmartFusion2 FPGA for Tier2 IPMI with HOST 3.0 support
- Native dual 10 GbE-KR ports
- 16 GB DDR4 @ 2133 mega-transfers per second (34 GB/s aggregate)
- XMC PCIe up to Gen3
- PCIe Gen3 on 3U OpenVPX data plane
- TrustedCOTS protections
- Variants aligned with the SOSA Technical Standard or E-OSA specifications are available
- Multi-mode Radar
- Synthetic Aperture Radar (SAR)
- Signal Intelligence (SIGINT)
- Electro-Optical/Infrared (EO/IR))
- Electronic warfare (EW)
- Mission computing
- Industrial server applications
CHAMP-XD1S SOSA-Aligned 3U VPX Intel Xeon D Processor Card
High-Performance 3U VPX Processor Card
Ideal for Radar, SIGINT, and EW Applications
For highly compute-intensive industrial, aerospace, and defense applications where security is critical, the CHAMP-XD1S digital signal processor (DSP) provides enhanced Trusted Computing features alongside leading-edge processing technology for unmatched performance.
- Aligned with the SOSA™ Technical Standard
- High-performance processing
- Trusted Computing capabilities
- High-speed data transport
This High-Performance Embedded Computing (HPEC) module delivers incredible processing capability by pairing an 8 or 12-core Intel Xeon D processor with a Xilinx MPSoC field programmable gate array (FPGA). And, its XMC mezzanine site allows system designers to add even more processing capability within a single slot. Ideal for ISR applications, such as SIGINT, EW, and SAR, the CHAMP-XD1S delivers impressive capability in a 3U VPX board.
Aligned with the SOSA Technical Standard
Choose from variants to support your specific requirements, including models developed in alignment with The Open Group Sensor Open Systems Architecture™ (SOSA) Technical Standard or E-OSA specifications.
The CHAMP-XD1S combines the high core count and floating-point performance of the Intel Xeon D processor with the substantial bandwidth and system-enabling features of the VITA 3U OpenVPX form-factor. As well, it includes a Xilinx ZU4EG FPGA with quad-core A53 processor and an XMC mezzanine site to add additional processing capability.
Trusted Computing Capabilities
The CHAMP-XD1S provides FPGA and software security features complemented by TrustedCOTS Enhanced Trusted Boot capabilities, including an FPGA-based Root of Security to protect against malicious cyber attacks, probing, and reverse-engineering.
High-Speed Data Transport
The CHAMP-XD1S supports 1 Gigabit (Gb) or 10 Gigabit Ethernet (GbE) interfaces along the OpenVPX control plane, as well as PCI Express Gen3 on the data plane. Its XMC mezzanine site adds even more configuration flexibility, with a myriad of mezzanine cards available from both Curtiss-Wright and other industry vendors.
What is the Open Group Sensor Open Systems Architecture Technical Standard?
The SOSA™ Technical Standard defines a common framework for transitioning sensor systems to an open systems architecture. The SOSA standard leverages OpenVPX to define card profiles with specifications for features such as pinouts, Ethernet capabilities, and serial ports.
Comprehensive protection throughout the product lifecycle
Curtiss-Wright goes well beyond standard approaches to Trusted Computing to provide truly secure solutions for air, ground, and sea platforms. We keep cybersecurity and physical protection in mind, from design and testing to supply chain and manufacturing. This comprehensive, end-to-end approach creates an effective mesh of protection layers that integrate to ensure reliability of Curtiss-Wright products in the face of attempted compromise.