Vanguard PCI-0-SL PCI/PCI-X Bus Analyzer, Exerciser, Protocol Checker, and Compliance Checker for 133MHz DUT
The Vanguard PCI-0-SL PCI-X Bus Analyzer allows testing in single-slot systems at up to 133 MHz, whilw isolating the PCI/PCI-X bus and uses a bridge to locate the Device Under Test from the backplane PCI/PCI-X bus. Devices can then be tested at full speed without introducing non-compliant electrical conditions to the system in use. Users should test systems with multiple devices using the companion product Vanguard PCI Bus Analyzer. The unit is controlled via USB, an Application Programming Interface (API), or Ethernet from a PC running Windows and BusView graphical user interface. With Ethernet connection, users can connect to the Vanguard analyzers at any network area location, adding many possibilities to the bus analyzer tool.
State Analyzer - With highly advanced (yet simple to use) triggering, filtering and counting capabilities, the Vanguard PCI State Analyzer captures and displays 64- or 32-bit PCI-X/PCI bus activity up to 133 MHz. The state analyzer's choice of three sampling modes - Standard Mode, Clock Mode & Transfer Mode--provides optimum bus analysis for both hardware and software debugging.
Exercisers - The Vanguard PCI-0-SL PCI-X Bus Analyzer's two flexible and easy to use Exerciser versions (basic and enhanced) allow concurrent operation of two DMA engines, a target memory with I/O and memory spaces, and a command executer. A flexible script feature allows users to make test scripts and to automate tasks.
Protocol Checker - The Curtiss-Wright (formerly VMETRO) Vanguard PCI-0-SL PCI-X Bus Analyzer's optional protocol checker for PCI-X and PCI automatically detects up to 71 PCI-X and 45 PCI protocol errors, helping the user to find bus hardware errors without understanding the problem's nature. While the state analyzer, the bus utilization statistics, and other Vanguard PCI analyzers are active, the protocol checker can run in the background, screening the bus for errors. If the protocol checker is used as the trigger source for the analyzer(s), the state and timing analyzers provide a comprehensive picture of the bus activity around the point when an error was found, helping the user to identify and correct the problem.
- REQUEST A QUOTE
- Fully compliant debugging of 133 MHz systems
- Concurrent and independent operation of all functions (analyzer, exerciser, protocol checker, and compliance checker)
- Optional Protocol Checker and Exerciser
- Networked Bus Analyzer (built-in Ethernet port) and USB
- 0-133 MHz PCI-X and 0-67 MHz PCI
- 2 MSample Trace Buffer at 256 bits
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