VPX3-450 3U VPX DSP Processor Card with Virtex-5 FPGA and 8640D Processor

The VXP3-450 3U VPX Digital Signal Processor is designed to be used in either a single-board configuration, or in multi-board configurations with other VPX3-450 boards or with the VPX3-127 Single Board Computer (SBC) using a high-speed PCI Express serial switching fabric. Utilizing the massive parallelism and rapid reconfigurability of Xilinx Virtex-5 FPGAs, combined with the flexibility of an AltiVec-enabled dual-core NXP (formerly Freescale) Power Architecture MPC8640 processor, the VPX3-450 DSP engine is well suited to replace either dedicated ASIC-based hardware or large arrays of processors for front-end signal or image processing, where sustained data rates and processing performance are important to overall system performance, or general algorithm acceleration tasks where data is pushed into the FPGA for calculation performance that may take 10's of general purpose processors to achieve. All platforms utilize Curtiss-Wright's Continuum Software Architecture (CSA) to insure compatibility and user code commonality across platforms.

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  • 3U VPX-REDI
  • One Xilinx Virtex-5 Platform FPGA (LX155T, or SX95T)  
  • 256 Mbytes DDR2 SDRAM attached to the FPGA, 2.2 GBytes/sec peak bandwidth
  • 18 Mbytes QDR-II+ SRAM attached to the FPGA in two banks, 4.4 GBytes/sec peak bandwidth per FPGA
  • 1 GHz NXP Power Architecture MPC8640D dual-core processor with 1 Gbytes of DDR2 SDRAM in two banks 
  • XMC mezzanine site
  • On-board PCI Express switch with 4-lane connectivity to the PowerPC, the FPGA, the mezzanine site, and a 4-lane port to the backplane
  • One additional 4-lane backplane fabric port to the PowerPC.  May be either PCI Express or Serial RapidIO
  • Two 4-lane MGT ports to the backplane
  • 256 Mbytes Flash for PowerPC or FPGA code or user files 
  • Support for ChipScope Pro and JTAG processor debug interfaces
  • Continuum FXtools developer's kit offers Continuum Firmware and BSP, 450-specific software libraries, BIT, highly-optimized IP blocks, reference designs, and a scriptable simulation testbench
  • Low and high temperature-qualified IP blocks
  • Air-cooled and conduction-cooled versions
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