CHAMP-WB/VPX6-474 6U OpenVPX Virtex-7
The CHAMP-WB is the first entry in Curtiss-Wright Defense Solutions’ family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded high-performance digital signal and image processing applications. The CHAMP-WB is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the TADF-4300 module, featuring 12 GS/s 8-bit ADC technology and 12 GS/s 10-bit DAC technology from Tektronix, an extremely high performance wide-band DRFM system can be created with is 3 times the capability of any COTS vendor. The combined card-set is called the CHAMP-WB-DRFM.
The CHAMP-WB couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with two high-bandwidth mezzanine sites on a rugged 6U OpenVPX (VITA 65) form factor module. The CHAMP-WB complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO® (SRIO). 10.3 Gbps Aurora links can also be supported between FPGA cards. Alternate fabrics can also be supported with different FPGA cores. A Gen3 PCI Express (PCIe) switch connected to the Expansion Plane provides a way for a single host card, such as the VPX6-1957 or CHAMP-AV8, to control multiple CHAMP-WB cards without utilizing dataplane bandwidth. Two 64-bit 4GB DDR3L memory banks provide 8 GB of on-card data capture or pattern generation capability. An auxiliary x4 SERDES link and 16 LVDS pairs provide additional I/O capability. The two mezzanine sites support standard FMCs and have an additional connector to provide enhanced bandwidth and capability. The extra connector provides at least another 48 differential pairs each as well as extra clocking, power and control signals. Running up to 600 MHz DDR, there is support for over 19GB/s of data I/O on each mezzanine site. Additional clocking and synchronization signals have been routed to the backplane to provide additional flexibility. Furthermore, one of the FMC sites has an option to take up to eight of the backplane SERDES and rout them to the mezzanine site to support new JESD204B serial I/O FMCs or Serial FMCs.
- REQUEST A QUOTE
- CHAMP-WB Xilinx Virtex-7 6U OpenVPX FPGA Processor Product Sheet
- CHAMP-WB-A25G Card Set Product Sheet
- CHAMP-WB-DRFM Xilinx Virtex-7 6U OpenVPX DSP with Tektronix 12 GS/s ADC/DAC Module Product Sheet
- CHAMP-WB-D25G Card Set Product Sheet
- CHAMP-WB Quick Start Kit Product Sheet
- Analog I/O & Receiver Summary
- White Paper: Understanding HPEC Computing - The Ten Axioms
- White Paper: High-performance Converters and VPX: Bridging the RF-to-Digital Divide
- White Paper: Fabric40 - An Introduction
- 04/23/13 - Curtiss-Wright Awarded Contract by Northrop Grumman
- COTS Boards Brochure
- OpenVPX (VITA 65) profile MOD6-PAY-4F1Q2U2T-12.2.1-11, VPX REDI (VITA 48 option)
- Single user-programmable Xilinx Virtex-7 FPGAs (X690T or X980T), with
- 8 GB DDR3L SDRAM in two banks
- Four 4-lane serial data plane links to the backplane (support up to 10.3 Gbps data rates)
- Gen2 SRIO or alternate fabrics with different FPGA cores
- One 4-lane Gen3 PCIe connection to a Gen3 PCIe switch
- One additional x4 10.3 Gbps link to the backplane
- 16 LVDS pairs to the backplane
- Two enhanced FMC interfaces with 128+ differential signal pairs
- One site supports JESD204B or Serial FMCs with up to 8 serial links
- The other site has optional support for up to 160 LVDS pairs with X690T FPGA
- One site supports JESD204B or Serial FMCs with up to 8 serial links
- Two Mezzanine sites with support for FMC (VITA 57) or enhanced FMC
- Onboard PCIe Gen3 switch - Two 8-lane expansion plane fabric ports to the backplane with configurable NTB support
- Sensors for monitoring board power consumption
- Support for ChipScope Pro and JTAG processor debug interfaces
- Backplane clock/sync paths to mezzanines sites
- FXTools BSP and FPGA design kit with highly-optimized IP Blocks, development environment, reference designs, scriptable simulation test benches and software libraries VxWorks and Linux variants available
- VITA 48 1" pitch format
- Ruggedization levels
- Air-cooled Level 0 (commercial)
- Conduction-cooled Level 200 (future)
- Path to variant with Processor (contact factory)
The ADC510 allows developers to integrate dual analog input channels into embedded computing systems. Conforming to the VITA 57 standard, the ADC510's inventive design makes a developer's job...
The ADC511 offers system developers a highly functional, cost-effective solution for directly connecting analog input with FPGA-based embedded processing nodes. The ADC511 belongs to the...
The ADC512 is part of the Curtiss-Wright series of modular I/O solutions that enable system developers to directly connect analog input with FPGA-based embedded processing nodes. The ADC512,...
The ADC513 enables system developers to connect analog input directly with FPGA-based embedded processing nodes. A part of the Curtiss-Wright VITA 57 FMC standard-compliant modular I/O solutions,...
The CHAMP-AV9 combines the floating point performance of the Intel Core i7 processors, with the substantial bandwidth and system-enabling features of the 6U OpenVPX form-factor. Providing a pair of...
The CHAMP-FX4 is the flagship 6U product in Curtiss-Wright Defense Solutions' family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs of challenging...
The OpenVPX CHAMP-WB/CHAMP-WB-DRFM/A25G/D25G 6U Quick Start Kit (QSK) from Curtiss-Wright Defense Solutions enables the system developer to rapidly prototype a core system for software and...
The CHAMP-WB-DRFM Digital RF Memory (DRFM) card is one of Curtiss-Wright Defense Solutions’ family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs...
The FMC-516, available in rugged air- and conduction-cooled variations, brings together the processing power of four synchronized 250 MSPS 16-bit ADCs and a local programmable clock in a VITA...
The FMC-518 is a quad channel 500 MSPS 14-bit analog input FPGA Mezzanine Card (FMC). The FMC (VITA 57) specification allows I/O devices to be directly coupled to a host FPGA. This makes the...
The inventive design of the FMC-520, which conforms to the VITA 57 FMC standard, simplifies developers’ integration of FPGAs and analog output into their embedded system designs. Depending on the...
The FMC-XCLK2 provides high-speed I/O products – including analog-to-digital converters – a variety of clock source options through as many as four synchronized sample clocks. Among the options...
HPEC is Curtiss-Wright's application of High-Performance Computing technologies to the rugged COTS computing market. HPEC (High-Performance Embedded Computing) includes many of the same data flow...
The VPX6-1958 rugged, high performance 6U OpenVPX Single Board Computer (SBC) combines Intel's powerful Core i7 processor with the power and flexibility of the VPX platform's high speed fabric...
The VPX6-1959 rugged, high performance 6U OpenVPX Single Board Computer (SBC) combines Intel's powerful Core i7 processor with the power and flexibility of the VPX platform's high speed fabric...
The VPX6-6802 is a combined Data Plane and Control Plane high-performance switch for small, mid-size and large 6U VPX systems. As part of the Curtiss-Wright Fabric40™ family of high-speed VPX...
The VPX6-6902 is a combined management, control and dataplane switch for small, mid-size and large 6U VPX systems. Supporting a centralized switch architecture in both star and dual-star...
Contact our sales team today to learn more about our products and services.
Our support team can help answer your questions - contact us today.