CHAMP-WB-A25G Xilinx Virtex-7 6U OpenVPX Wideband Receiver with 25 Gsps ADC
The CHAMP-WB is one of Curtiss-Wright's family of user-programmable Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded high-performance digital signal and image processing applications. The CHAMP-WB is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the 25 Gsps ADC module, featuring 25 Gsps 8-bit ADC technology from Tektronix, an extremely high performance wide-band receiver can be created. The combined card-set is called the CHAMP-WB-A25G and joins the other members of the CHAMP-WB product family.
The CHAMP-WB-A25G couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with a high-bandwidth 25 GS/s 8-bit ADC module in a commercial grade 6U OpenVPX (VITA 65) form factor module. The 25G ADC module can also operate in a dual channel 12.5 GS/s mode. The CHAMP-WB-A25G complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO (SRIO) or Aurora up to 10.3 Gbps. Alternate fabrics can also be supported with different FPGA cores. A Gen3 (PCIe) switch connected to the Expansion Plane provides a way for a single host card, such as the VPX6-1957/1958, CHAMP-AV8 or CHAMP-FX4 to control multiple card sets in the CHAMP-WB product family, without utilizing data-plane bandwidth. Two 64-bit 4 GB DDR3L memory banks provide 8 GB of on-card data capture capability. An auxiliary x4 SerDes link and 16 LVDS pairs provide additional I/O capability.
The 25 Gsps ADC module is made up of a front-end track & hold device with 15+ GHz bandwidth which feeds two 12.5 Gsps ADC multi-chip-module (MCM) devices. Each of the ADC devices present 128 LVDS pairs of data to the FPGA. The track & hold device can either interleave, replicate, or provide two independent data streams to the ADC devices depending on the processing desired. A 100 MHz reference clock is generated on card or can be supplied by the backplane to the ADC device. For optimal performance an RTM with a 3 ppm clock is available which can also distribute the clock to multiple cards. The clock is locally filtered to generate a clean sample clock on the mezzanine for the ADC device. The sampling clock can be adjusted with kHz resolution. In addition the base card supplies the primary power to the ADC module. The FPGA utilizes an I2C and SPI interface to the ADC module, to configure the module, calibrate the ADC device and retrieve status.
An FPGA reference design is provided which includes FPGA IP and SW for all of the peripheral interfaces as well as for calibrating and capturing data on the ADC interface.
- REQUEST A QUOTE
- OpenVPX (VITA 65) MOD6-PER-4F-12.3.1-8; MOD6-PER-1Q-12.3.5-2 VPX REDI (VITA 48 option)
- Single user-programmable Xilinx Virtex-7 FPGAs X690T, with 8 GB DDR3L SDRAM
- Single-channel 25 Gsps, dual-channel 12.5 Gsps 8-bit ADC
- 20 x backplane SerDes capable of 10.3 Gbps each
- Onboard PCIe Gen3 switch
- Electronic warfare
- Radar processing
- Signal Intelligence (SIGINT)
- Wideband communications
- Image processing
- Sensor processing
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