CHAMP-WB-D25G Xilinx Virtex-7 6U OpenVPX Wideband Transmitter with 25 Gsps DAC
The CHAMP-WB is one of Curtiss-Wright’s family of user-programmable Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded high-performance digital signal and image processing applications. The CHAMP-WB is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the 25 Gsps DAC module, featuring 25 Gsps 10-bit DAC technology from Tektronix, an extremely high performance wide-band transmitter can be created. The combined card-set is called the CHAMP-WB-D25G and joins the other members of the CHAMP-WB product family.
The CHAMP-WB-D25G couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with a high-bandwidth 25 GS/s 10-bit DAC module in a commercial grade 6U OpenVPX (VITA 65) form factor module. The CHAMP-WB-D25G can also be used in conjunction with the CHAMP-WB-A25G companion 25 Gsps ADC card set to create a very high performance wide band communications, EW or sensor processing system. The CHAMP-WB-D25G complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO (SRIO) or Aurora up to 10.3 Gbps. Alternate fabrics can also be supported with different FPGA cores. A Gen3 (PCIe) switch connected to the Expansion Plane provides a way for a single host card, such as the VPX6-1957/1958, CHAMP-AV8 or CHAMP-FX4 to control multiple card sets in the CHAMP-WB product family, without utilizing data-plane bandwidth. Two 64-bit 4 GB DDR3L memory banks provide 8 GB of on-card pattern generation capability. An auxiliary x4 SerDes link and 16 LVDS pairs provide additional I/O capability.
The Virtex-7 FPGA is connected to the DAC silicon via a 160 LVDS pair interface. Due to the interface speed, a -3 (fastest) speed grade FPGA is required. A 100 MHz reference clock is generated on card or can be supplied by the backplane to the DAC device. The clock is locally filtered to generate a clean sample clock on the mezzanine for the DAC device. The sampling clock can be adjusted with kHz resolution. In addition the base card supplies the primary power to the DAC module. The FPGA utilizes an I2C and SPI interface to the DAC module, to configure the module, calibrate the DAC device and retrieve status.
An FPGA reference design is provided which includes FPGA IP and SW for all of the peripheral interfaces as well as for calibrating and transmitting data on the DAC interface.
- REQUEST A QUOTE
- OpenVPX (VITA 65) MOD6-PER-4F-12.3.1-8; MOD6-PER-1Q-12.3.5-2 VPX REDI (VITA 48 option)
- Single user-programmable Xilinx Virtex-7 FPGAs (X690T), with 8 GB DDR3L SDRAM
- 25 Gsps, 10-bit DAC
- 20 x backplane SerDes capable of 10.3 Gbps each
- Onboard PCIe Gen3 switch
- Electronic warfare
- Electronic attack
- Wideband communications
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