CHAMP-WB-DRFM Xilinx Virtex-7 6U OpenVPX Card with Tektronix 12 Gsps ADC/DAC Module
The CHAMP-WB-DRFM Digital RF Memory (DRFM) card is one of Curtiss-Wright Defense Solutions’ family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded high-performance digital signal and image processing applications. The CHAMP-WB is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the 12 Gsps ADC/DAC module, featuring 12 Gsps 8-bit ADC technology and 12 Gsps 10-bit DAC technology from Tektronix, an extremely high-performance wide-band DRFM system can be created. The combined card set is called the CHAMP-WB-DRFM.
The CHAMP-WB-DRFM couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with a high-bandwidth 12 Gsps 8-bit ADC and 12 Gsps 10-bit DAC module in a commercial grade or rugged 6U OpenVPX(VITA 65) form factor module. The ADC device can also operate in a dual channel mode, up to 6 Gsps. The CHAMP-WB-DRFM complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO (SRIO). Alternate fabrics can also be supported with different FPGA cores. A Gen3 PCI Express (PCIe) switch connected to the Expansion Plane provides a way for a single host card, such as the VPX6-1957/1958 or CHAMP-AV8, to control multiple CHAMP-WB-DRFM card sets without utilizing data-plane bandwidth. Two 64-bit 4 GB DDR3L memory banks provide 8 GB of on-card data capture or pattern generation capability. An auxiliary x4 SerDes link and 16 LVDS pairs provide additional I/O capability.
The 12 Gsps ADC device goes through a pair of DEMUX devices presenting a 128 LVDS pair interface to the Virtex-7 FPGA. In parallel, a separate 160 LVDS pair interface connects the FPGA to the DAC device. A 100 MHz reference clock is generated on card or can be supplied by the backplane to both the ADC and DAC device. The clock is locally filtered to generate a clean sample clock on the mezzanine for both the ADC and DAC device. The sampling clock can be adjusted with kHz resolution. There is also precise fractional clock support. In addition the base card supplies the primary power to the ADC/DAC module. The FPGA utilizes an I2C and SPI interface to the ADC/DAC module, to configure the module, calibrate the ADC/DAC devices and retrieve status.
An FPGA reference design is provided which includes FPGA IP and SW for all of the peripheral interfaces as well as for calibrating the ADC/DAC interface, capturing data on the ADC interface and transmitting data on the DAC interface.
- REQUEST A QUOTE
- Analog I/O & Receiver Summary
- CHAMP-WB Xilinx Virtex-7 6U OpenVPX FPGA Processor Product Sheet
- CHAMP-WB Quick Start Kit Product Sheet
- White Paper: High-performance Converters and VPX: Bridging the RF-to-Digital Divide
- White Paper: Fabric40 - An Introduction
- White Paper: Understanding HPEC Computing - The Ten Axioms
- COTS Boards Brochure
- OpenVPX (VITA 65) profile MOD6-PAY-4F-12.3.1-8; MOD6-PER-1Q-12.3.5-2, VPX REDI (VITA 48 option)
- Single user-programmable Xilinx Virtex-7 FPGAs (X690T or X980T), with 8 GB DDR3L SDRAM
- 12 Gsps (or dual 6 Gsps) 8-bit ADC and 12 Gsps 10-bit DAC
- 20 x backplane SerDes capable of 10.3 Gbps each
- Onboard PCIe Gen3 switch
- Electronic warfare
- Radar processing
- Signal Intelligence (SIGINT)
- Wideband communications
- Image processing
- Sensor processing
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