Digital Down Conversion (DDC)
Digital Down Conversion (DDC) FPGA IP cores are available supporting Xilinx Virtex-5, Virtex-6 and Virtex/Kintex-7 FPGAs. The DDC family of IP cores support decimation from 2 to 64 in complex mode and from 2 to 32 in real mode. The DDC is available as embedded IP within a number of Curtiss-Wright ADC products or in a source format.
The DDC supports the following products:
Benefits of Curtiss-Wright DDC products include reduced application development time, fully-tested and documented HDL components, east integration with other application HDL and complete Digital Down Converter (DDC) I/O.
Curtiss-Wright offers the DDC001 as an IP package that users can integrate with their own application code. The DDC001 arrives with HDL source code, test bench and full user documentation. The toolchain used for creating the IP is Xilinx ISE 10.1.3 and ModelSim 6.3. As an option, the XMC-E2201 and XMC-E2202 may be ordered with pre-integrated DDC functionality, enabling the board to operate as a wideband DDC. Documentation is included with this option.
The Curtiss-Wright DDC001 is a Wideband Digital Down Converter (DDC). It delivers functionality similar to that of GC1012B from TI. It supports output bandwidth of Fs/4 to Fs/128 with a complex output and Fs/2 to Fs/64 with a real output. The DDC001 operates in excess of 250MHz in a -2 speed grade Xilinx Virtex-5 SX95T.
DDC001 permits scaling of the input signal by up to 72dB with a granularity of 0.03dB and gain at a 20-bit input with an 8-bit fractional part. The Input Gain Block is designed with an overflow output. As appropriate, the output from this block will saturate to the maximum positive or negative value.
The NCO of the DDC001 features 21-bit outputs to the mixer and a 32-bit accumulator. It provides a 120dB SFDR using phase dithering and Taylor series correction. The NCO also supports an 11-bit phase offset.
The DDC001’s Mixer takes a real input from the Input Gain Block and multiplies it with the Cos and –Sin inputs from the NCO to produce a complex output that it passes to the Decimating FIR filter, which supports decimation rates of 2, 4, 8, 16, 32 and 64. The user can program all four sets of filter coefficients. Two sets come pre-programmed with coefficients that support passbands of 80% and 90% of the output bandwidth. However, the pre-programmed filter sets may be reprogrammed at runtime. And filter sets other than the one in use may be updated at runtime without disturbing the operation of the filter.
- REQUEST A QUOTE
- Xilinx Virtex-5, 6 or 7 FPGA support
- 16-bit input
- NCO with 32-bit tuning word, 120dB SFDR
- 18-bit or 24-bit coefficients
- Four independent programmable coefficient sets
- Up to 2560 filter taps
- Complex or real outputs
- Decimation of 2, 4, 8, 16, 32 or 64 (complex)
- Decimation of 1, 2, 4, 8, 16 or 32 (real)
- Output formatting to 16-bits or 24-bits
- Output spectrum can be inverted or shifted by Fo/2
- Modular design supporting customization for specific requirements e.g. more or fewer
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