ADX000 Virtex-5 PMC/XMC

The ADX000 is a high performance FPGA processing PMC or XMC. The combination of a user-programmable FPGA and multiple banks of fast memory provides a powerful platform for an FPGA-based co-processor, acquiring and processing high-speed data in one board. In addition to processing, the Xilinx Virtex-5 SXT or LXT FPGA is used to drive the off-board interfaces to either PCI-X or the multi-Gbps serial I/O used for the XMC interface. The ADX000 is a sister product to AD1520 and AD3000, which incorporate dual 1.5 or single 3.0 GSPS ADCs.

The ADX000, a second generation XMC module, provides the majority of the Virtex-5 FPGA's resources for user-programmable processing, supported by SRAM and SDRAM. Applications ideally suited for FPGA include Digital Down Conversion (DDC), Fast Fourier Transforms (FFTs) and digital filters.

The ADX000 can be fitted with a Xilinx Virtex-5 SX95T or LX110T FPGA. Contact Curtiss-Wright for information on the availability of other FPGA variants. The ADX000's design allows for optimization of DSP capabilities and logic gates.

The ADX000 provides external SRAM and SDRAM connected to the FPGA for data buffering or general purpose processing support. The two 128 MB DDR2 SDRAM banks can be used in parallel to buffer digitized data. Each 16-bit wide bank is clocked at up to 250 MHz for a net storage rate of up to 1 GB/s per bank. 

Higher bandwidth external memory is available through QDR2 SRAM. It features two 2 MB x 36-bit banks, which are clocked at 200 MHz, netting a throughput of up to 2 GB/s per bank. 

The ADX000 includes a PCI/PCI-X interface that supports operation of up to 133 MHz. It also includes a PCIe interface. Both interfaces provide multi-channel DMA support. 

The PCIe interface of the ADX000 utilizes Virtex-5 FPGA RocketIO GTP transceivers and an embedded end-point controller, which serves as a hard IP block within the Virtex-5 FPGA. In accordance with the PCIe standard, the PCIe endpoint block supports x4 or x8 lane communications at 2.5 GB/s. However, the end point block can be bypassed to support other protocols such as Serial RapidIO (SRIO) or sFPDP. 

Through RocketIO GTP transceivers, the Virtex-5 FPGA provides 16 full duplex high-speed serial communication links, divided evenly between two XMC (VITA 42) connectors. Each link is capable of operating at up to 3.2 GB/s (using an SX95T FPGA) and may be driven as independent data streams or may be consolidated to form fat pipes, resulting in fewer, but higher bandwidth, data streams. 

The ADX000A is designed to handle a range of environmental requirements: air-cooled benign, air-cooled extended temperature, air-cooled rugged, and conduction-cooled. For conduction-cooled applications, the host board must be able to incorporate front panel I/O connections. Depending on the application, a suitable heatsink may be required for conduction-cooled builds.

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  • Xilinx Virtex-5 LX110T or SX95T FPGA (user programmable)
  • Two banks 128Mbyte 250MHz 16-bit DDR2 SDRAM and two banks 4.5Mbyte 200MHz 36-bit QDR2 SRAM memories
  • XMC/PMC Form factor (including rugged)
  • Windows, VxWorks and Linux support
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