MM-6171 XMC 2-8GB

The MM-6171 Buffer Memory XMC supports Serial RapidIO (sRIO) x4. Equipped with 2,4, or 8GB of DDR2 SDRAM, the Buffer Memory XMC provides high-speed buffering capabilities for DSP systems. The XMCs have a variety of uses, such as high-speed temporary storage, expanded system memory, interleaving, or for use with data aggregation and warehousing. The DDR2 SDRAM provides superior performance with low latency, while the bus interface with it's full-featured DMA engine allows transactions to occur without host intervention.

Conforming to the VITA 42 mezzanine standard, the MM-6171 Buffer Memory XMC interfaces to the host through the P15 connector. The card supports from four to eight HSS links running at up to 3.125GHz to provide a high-speed full duplex interface. Connecting these high-speed signals to the memory arrays is a Xilinx Virtex-5 LX110T FPGA. The device functions as a memory controller and is not designed to host User Programmable Logic. Off of the FPGA are two independent memory arrays, each capable of interfacing to 1, 2, or 4GB of DDR2 memory. Single-bit errors are corrected and double-bit errors are detected through the memory controller logic. The DDR2 arrays provide over 3GB/s of data bandwidth.

The MM-6171 Buffer Memory XMC also includes a fully verified bus interface and DMA engine. With SRIO, each link of the x4 bus interface runs at 3.125GHz. The SRIO DMA engine is a corner-turning, striding DMA engine, providing advanced functionality for DSP designs.

The MM-6171 Buffer Memory XMC supports both Wind River VxWorks and Wind River GPP Linux 2.6.x with the appropriate device driver.

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  • 2,4 or 8 GB High-speed DDR2 SDRAM
  • 4x Serial RapidIO
  • Full-featured DMA engine
  • Rugged convection and conduction-cooled versions
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