FMC-516 Quad 250MSPS 16b ADC FMC

The FMC-516, available in rugged air- and conduction-cooled variations, brings together the processing power of four synchronized 250 MSPS 16-bit ADCs and a local programmable clock in a VITA 57-compliant FMC format. The density, speed and resolution of the data delivered to the FPGA host provides low latency, high-performance functionality necessary for applications such as Signal Intelligence (SIGINT), Electronic Counter Measures (ECM) and Radar (including beamforming). The FMC-516 can be synchronized multiple FMC-516 modules to promote coherent sampling. The module has three options for delivering sample clock input source. These include an external RF clock input that provides direct sampling frequency, a 10MHz external reference, and an internal source that drives an onboard programmable clock generator.

The FMC-516 minimizes latency and maximizes data throughput as its four ADC devices connect by way of a high bandwidth FMC connector to the FPGA-based host board. Trigger input/output signals controlled by the FPGA can synchronize multiple FMC-516 boards to increase the number of input channels. The FMC-516 is ideal for platforms such as the FPE650 (quad Xilinx Virtex-5), HPE720 (MPC8641D/dual Virtex-5), FPE320 (Xilinx Virtex-5) or VPX6-473 CHAMP-FX4 (Xilinx Virtex-7).

For the external 10 MHz reference option, the sample clock is derived from the onboard programmable clock generator, which the 10 MHz source drives. A 50Ω LVPECL input, the external sample clock operates at an input level of 0 dBm to + 8dBm. The minimum sample clock supported by the FMC-516 ADCs is 80 MSPS and may be sinusoidal or square.

Trigger In and Trigger Out signals of the FMC-516 use MMCX-type front panel connectors. The operation of these signals depends on the HDL code in the FPGA host carrier card. Trigger In and Trigger Out are single-ended LVPECL-buffered signals that are connected to the host FPGA. Using appropriate HDL code the Trigger In and Trigger Out signals can be used to synchronize the ADCs of multiple FMC-516s. User-developed HDL can be used for applications that do not require Trigger capability.

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  • Analog Input:
    • Number of Channels:  4, single-ended
    • Sampling Frequency:   Up to 250MSPS
    • Full Scale Input Voltage:   18.8 dBm
    • Device:   4x Intersil ISLA216P25
    • Input Bandwidth (3dB): up to 500 MHz
    • SFDR (at 105 MHz): 84 dBFS (typ)
    • SNR (at 105 MHz): 70 dBFS (typ)
    • ENOB (at 105 MHz): 11.3 bits (typ)
    • Input Impedance: 50 Ohm, AC coupled
    • Input Connector: Front panel MMCX
  • Sample Clock:
    • Connector: Front panel MMCX
    • Input impedance: 50 Ohm, AC coupled LVPECL
    • Clock Input: 40-250 MHz (RF) or 10 MHz reference input
  • Internal clock  selectable from:
    • SiLabs Si571 programmable clock (frequency range 40 - 250 MHz)
    • Programmable clock source (10MHz - internal or external)
    • Configure by FPGA
  • Software/HDL Code:
    • FusionXF software/HDL tools for Xilinx Virtex-6/7 hosts
  • Environmental:
    • Ruggedization levels:  Air-cooled level 0 and level 100, conduction-cooled level 200
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