TADF-4300 12GSPS ADC/DAC Enhanced FMC
The TADF-4300 Series Enhanced FMC Mezzanine card contains a two channel ADC that utilizes the Tektronix HFD204 SiGe ASIC and a single channel DAC utilizing a Tektronix SiGe ASIC. The output of the HFD204 is 32 SERDES pairs at a clock rate of 3.125 Gb/s and is processed by a pair of Tek020 demultiplexers operating in 1:4 mode. The resulting output is a 128-bit LVDS datastream at 750mb/s DDR (dual data rate, at 12 GS/s) and is presented to the FPGA via 128 LVDS pairs. The DAC is interfaced via 160 LVDS pairs on the second enhanced FMC interface and can accept data at up to 750 Mb/s per LVDS pair, for a DAC output rate of 12 GS/s. Since the ADC and DAC share a common clock, the maximum update rate of the ADC and DAC is limited to 12 Gs/s when operating both ADC and DAC in a DRFM type application. Both ADC and DAC sections have auxiliary SPI and I2C interfaces for control, register access and environment monitoring.
The TADF-4300 ADC section contains circuitry that enables the HFD204 ADCs to be accurately calibrated to minimize interleave spurs caused by poorly aligned sample clocks. The calibration is required on power up and is transparent to the user, requiring no front panel inputs. The calibration algorithms are also able to adjust for changes in operating temperature that would otherwise degrade performance.
The Mezzanine card is designed to mate with the Curtiss-Wright CHAMP-WB (VPX6-474) base board which provides power, and digital data interconnects to and from the mezzanine card. This card set is called the CHAMP-WB-DRFM. The interface connection between the mezzanine card and the base board is comprised of an FMC standard connector plus an auxiliary connector which contains additional data lines.
Learn more about this technology by watching the High Performance ADC & DAC Solutions with Reconfigurable DSP for Sense & Response Applications Webcast
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- Features Tektronix SiGe ASICs to support high resolution, high bandwidth signal acquisition and generation
- Double-wide Enhanced FMC module
- 12 GSPS 8-bit Analog to Digital Converter
- 12 GSPS 10-bit Digital to Analog Converter
- Onboard programmable sample clock
- Onboard calibration
- Reference clock input to support multi-channel synchronization
- Streaming interface to host FPGA for continuous full-rate acquisition applications
- Includes FPGA IP and software for data capture/generation, calibration and status collecting for ADC/DAC module
- Air-cooled and Conduction-cooled versions
The CHAMP-WB-DRFM Digital RF Memory (DRFM) card is one of Curtiss-Wright Defense Solutions’ family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs...
The CHAMP-WB is the first entry in Curtiss-Wright Defense Solutions’ family of user-programmable Xilinx Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded...
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