XCLK1 Multi-Channel Clock Generator

The XCLK1 high-frequency clock generator is a PMC/XMC module that provides high-speed I/O resources including analog-to-digital converters and as many as six synchronized sample clocks. The XCLK1, created specifically for embedded computing, offers users a range of clock source options, such as off-board RF, off-board 10 MHz references or an internal temperature-compensated crystal oscillator. The XCLK1 runs at frequencies up to 3 GHz.

The 10 MHz reference sources drive the XCLK1's low-phase noise VCO/PLL frequency multiplication circuitry. Curtiss-Wright offers each available frequency output as a build variant. Through local frequency multiplication, the 10 MHz temperature compensated crystal oscillator generates output signals from less than 100MHz to more than 3 GHz with a jitter of less than 0.5ps. The XCLK1 supports single-ended and differential clock outputs.

The XCLK1 is designed to synchronize the start of data acquisition for all available cards so that multiple samples across various ADC or DACs are coherent. It does this through its ability to momentarily interrupt all sample clock outputs with its trigger/reset input, giving all acquisition cards the necessary time to be reset and capture data synchronously.

The XCLK1 is designed and manufactured on Curtiss-Wright's more than 20-year tradition of advancing the performance and reliability of embedded computing components and systems for the harsh operating environments of aerospace and defense applications. At Curtiss-Wright, we continually expand our product range of analog I/O and digital receivers that are engineered for optimal performance in temperature extremes and vibration conditions.

Curtiss-Wright has advanced the use of FPGAs in digital signal processing systems to help developers realize the full potential of FPGAs through Digital Down Converters (DDCs), FFTs, filters, pulse compressors, data encryption and decryption for applications such as radar, signal intelligence and image processing.

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Six Channel 105 MSPS, 14-bit A/DC with dual RACE++
Six 14-bit 105 MHz A/D channels
Dual RACE++ interfaces on P2
Capacity: 2GB, 4GB, 8GB
VME64 master/slave interface
On-board 350 MHz Motorola PowerPC processor with 128 MB local SDRAM
On-board Gigabit Ethernet
Up to 32MB Programmable Flash
  • Ultra Low Jitter Multi-Channel Clock Generator
  • Up to six phase matched RF outputs (three differential)
  • Selectable internal or external 10 MHz reference (with frequency multipliers for RF output)
  • External RF clock source
  • XMC/PMC format (power only)
  • Air-cooled and rugged build options
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