LVDS-MOD3 32x LVDS module

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  • 64 I/O lines routed as 32 differential pairs
  • 68-way SCSI-3 style front panel connector
  • Mixed voltage signalling
  • FPGA Firmware blocks supplied in VHDL for integration into user applications
  • Windows, VxWorks and Linux host PMC support
LVDS-MOD4 64x LVDS module

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The LVDS-MOD3 is a front panel mezzanine module designed to provide LVDS I/O functionality to Curtiss-Wright's FPGA-based processing PMC modules. This LVDS I/O module provides 32 differential pairs to the front panel. The LVDS-MOD3 LVDS I/O module is aimed at embedded application development.

The LVDS-MOD3 LVDS I/O module is one of a range or modules for use with Curtiss-Wright PMC-FPGA05/XMC-FPGA05D Xilinx Virtex-5 FPGA PMC modules. These I/O modules allow flexibility in I/O to the host PMC/XMC module and directly connects the I/O to the FPGA, removing bottlenecks and providing an integrated processing solution.

Through this configuration, the host FPGA defines all impedances, timing and data flow. By way of a compliant pin-out, signals are routed to a SCSI-3 connector, allowing use of off-the-shelf differential SCSI-3 cables. This feature simplifies system development and reduces cost.

These I/O modules are designed for an array of applications including RADAR/LIDAR, electronic warfare, signal intelligence (SIGINT), surveillance, real-time imaging/inspection/machine vision, medical imaging and satellite modems.

The modules' simple design - consisting of analog converters or transceivers, buffers and connectors - simplifies the development of new application-specific modules.

The host connector of these modules supplies up to 138 signals, connecting them directly to the FPGA and routing them as LVDS pairs. This setup optimizes data speed and flexibility as the FPGA determines the interface characteristics such as impedance. Depending on the host board's capabilities, four of these digital I/O pairs can be local or global clock signals.

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