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- Dynamic shared-memory addressing
- Custom SIMM memory upgrade option
- Supports bus-level interrupt INTA
- Virtual paging for Shared Memory (CSR selectable)
- Variable-length message packet capability
- Dual-port memory
- Dual memory and error interrupt
- General-purpose Counter
- Error Interrupt Mask
- Single-Slot Solution
- 32-bit PCI compliant
- Maximum bus clock speed is 33 MHz
- Less than 1.5 amps @ 5 volts only.
- A ring topology with 150 Mb/s line transmission rate.
- A "Data-Filter" that allows only data stored in shared memory that has changed to be passed to the network for communications to the other nodes.
- No operating or system software required to support network protocol.
- No network-dependent application software required.
- BURST Mode protocol (Error Correction Disabled) with fixed-length message packets of 82-bits.
- BURST PLUS Mode communication based on variable packet size to a maximum of either 256 bytes or 1024 bytes.
- PLATINUM Mode protocol (error correction enabled) with fixed-length message packets of 82-bits.
- PLATINUM PLUS Mode communication based on variable-length message packet size to a maximum of either 256 bytes or 1024 bytes.
- 256-node capacity on each ring.
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SCRAMNet+ SC150/SC150e Shared Memory PCI, PMC, and VME Boards
The SCRAMNet+ product line is being discontinued. Please download the SCRAMNET+ EOL Notice to see last time buy, last shipment and repair information. Please consider the SCRAMNet GT200 as a possible migration path.
Curtiss Wright Defense Solutions provides a real-time communications network based on the concept of replicated, shared memory, knows as the SCRAMNet+ SC150e Network.
Host providers of the network have access to individual, local copy of shared memory, which is updated over a serial-ring network. The high-speed network is optimized for quick transfer of data among multiple, real-time computers who simultaneously find solutions. in real-time.
The SCRAMNet+ SC150e family of cards are reverse-compatible with Curtiss-Wright original SCRAMNet Classic product, SCRAMNET+, except for the GOLD RING communication.
To enhance performance, The SCRAMNet+ SC150e products use an architecture where shared memory read operations bypass the SCRAMNet ASIC. DMA operations will have the greatest increase in performance in addition to better PIO and DMA operations. The overall performance becomes more effective as read latency is reduced, the number of PCI retries is decreased, and the PCI bus utilization is improved.
The SCRAMNet+ SC150e board requires a single slot in the computer chassis.
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