CHAMP-XD2 6U VPX Intel Xeon D DSP Processor Card
The 6U OpenVPX CHAMP-XD2 rugged DSP engine module is designed for use in very compute-intensive Industrial, Aerospace and Defense applications, enabling developers of High Performance Embedded Computing (HPEC) systems to take full advantage of the unmatched performance of today’s leading-edge Xeon processor D architecture.
The CHAMP-XD2 combines the high core count and floating-point performance of the latest Intel Xeon D processors with the substantial bandwidth and system-enabling features of the VITA 6U OpenVPX form-factor. Providing a pair of extended temperature Intel Xeon D processors with 8 or 12 core processors each, the CHAMP-XD2 has a peak performance of >800 GFLOPS or >1100 GFLOPS respectively. This is coupled with 32 GB of high capacity DDR4-2133 per processor, with a bandwidth of >17 GBps per channel with two channels per processor.
For high speed data transport, the CHAMP-XD2 supports 1 Gigabit (Gb) or 10 Gigabit Ethernet (GbE) interfaces along the OpenVPX control plane in addition to 40G/10G Ethernet or InfiniBand on the data plane. The CHAMP-XD2’s XMC mezzanine site (designed for up to 25W of thermal dissipation) adds even more configuration flexibility, with a myriad of mezzanine cards available from both Curtiss-Wright and other industry vendors.
The CHAMP-XD2 is available in a range of ruggedized configurations to deliver optimal performance in the harshest deployed environments, including air-cooled and conduction cooled variants. There is also resident a Core Function field programmable gate array (FPGA) used for Trusted COTS™ security and general purpose I/O in addition to a dedicated Intelligent Platform Management Interface (IPMI) FPGA used for system monitoring and health.
The CHAMP-XD2 is supported by a suite of firmware, Operating Systems(OS), communication Application Programming Interfaces (APIs) and signal processing libraries. In particular, the OpenHPEC™ Accelerator Suite is Curtiss-Wright’s software environment of integrated OS with board specific drivers, optimized messaging and data movement middleware, and high performance computational libraries. Developers of mixed systems will find a common set of features and software interfaces for all future processing products from Curtiss-Wright.
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- CHAMP-XD2 Product Sheet
- White Paper: Deployable Core Counts Explode with Intel's Xeon D Processor
- Dolphin PCIe Fabric Communications Library Data Sheet
- Dual processor Xeon D 8-core (820 GFLOPS @ 1.6 GHz total) or 12-core (1152 GFLOPS @ 1.5 GHz total)
- Extended operating temperature Intel eTEMP SKUs
- PCH integrated in Xeon D SoC
- Four ports of 40G/10G Ethernet or DDR/QDR/FDR10 InfiniBand on OpenVPX data plane
- Native dual KX 1 GigE or KR 10 GigE ports on OpenVPX control plane
- 16 to 32 GB DDR4 @ 2133 megatransfers per second per Xeon D socket (68 GB/s aggregate)
- XMC PCIe up to Gen 3, designed for up to 25W thermal dissipation
- Dual x16 PCIe Gen 3 on OpenVPX expansion plane with switch
- Core Function FPGA with IPMI
- Conduction and air-cooled
- Multi-mode Radar
- Synthetic Aperture Radar (SAR)
- Signal Intelligence (SIGINT)
- Electro-Optical/Infrared (EO/IR)
- Electronic Warfare (EW)
- Mission computing
- Industrial server applications
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