High Speed Signal Integrity Capabilities

High Speed Signal Integrity Capabilities

Introduction

Curtiss-Wright Defense Solutions is a leader in the implementation of high-speed serial fabric signaling on VPX/OpenVPX platforms. We have been there every step of the journey:

  • From the introduction of VPX with Gen 1 protocols (e.g. Serial Rapid IO @ 2.5-3.125 Gbaud, PCI Express Gen 1 @ 2.5 Gbaud)
  • To Gen 2 (e.g. Serial Rapid IO @ 5-6.25 Gbaud, PCI Express Gen 2 @ 5.0 Gbaud)
  • Through Gen 3 (40G Ethernet @ 10.3125 Gbaud, Infiniband QDR @ 10.0 Gbaud, PCI Express Gen 3 @ 8 Gbaud)

Developing, introducing and deploying world-leading products at each stage. Work on Gen 4 (PCI Express @ 16 Gbaud) has been ongoing for more than a year, and product timing will be coordinated with silicon availability, among other factors.

Implementation

Implementation of Gen 1 and, to some extent, Gen 2 was relatively straightforward since the VPX connector and infrastructure were designed and rated for these speeds. With Gen 3 came more challenges, in particular the limitations of the VPX connector system such as the relatively high cross-talk at the via footprints of the module and backplane connectors. Curtiss-Wright recognized these limitations very early and worked closely with partners to ensure they could be mitigated when using Gen 3 signaling speeds. We performed extensive signal integrity (SI) simulation and analysis work to understand which mitigations worked, and by what margin.

These improvements form the basis of our module and backplane design rules for Gen 3, and substantial testing has shown that they work with enough margin to continue to use the standard VPX connector system (see the following representative data).

 

Fabric40 Typical SI “Torture Test”

High Speed Signal Integrity Capabilities

Figure 1: Equipment Tested

Download the white paper to learn more.

  • High Speed (Gen 3) Fabric Implementation
  • Next Gen VPX