When each component in the drive system is purpose-built for aiming and stabilization, integrated by experienced engineers, and proven in numerous field applications, system integrators can rest easy knowing their solutions will meet performance requirements

Safety certification for military embedded systems can be time consuming, complex, and costly to complete. Curtiss-Wright offers an extensive catalog of safety-certifiable COTS hardware modules to suit application requirements.

Hypersonic platforms provide a challenge for flight test campaigns due to the application’s flight profiles and environments.

Operators of aircraft may find they need to upgrade existing flight recorder for a variety of reasons.

This white paper examines how building a system with a dissimilar redundant architecture can help overcome the challenges of meeting DO-254/178 DAL A requirements.

Review the challenges for deploying QR encryption and how to implement DAR and data-in-transit QR encryption solutions using commercial FPGA devices and off-the-shelf hardware.

The goal of post-quantum cryptography is to develop cryptographic systems that are secure and can interoperate with existing communications protocols and networks.

The goal of reducing the cost of equipping Army vehicles with new capabilities, while adding increasing interoperability and flexibility of operation, can be accomplished through the use of a Modular Open Systems Approach (MOSA), a technical and business strategy for designing an affordable and adaptable system.

There is a popular industry misconception that Intel processors draw more power than Power Architecture and Arm processors. This paper discusses how that is not the case.

This white paper looks at how NetBoot brings new efficiencies, better security, and significant savings to teams that are tasked with maintaining software on embedded systems.

Gain valuable insights into NSA High Assurance Type 1 encryption including device consideration factors, encryption algorithms, and certification processes.

This white paper examines the key challenges multi-core processors present in safety-certifiable systems, and the traditional and newer, more effective techniques for alleviating them to ensure MCP-based systems will safely perform their intended functions.