Bringing Switched Fabric Technology to the Mezzanine Card Form Factor
The PMC (PCI Mezzanine Card) was first adopted for use in commercial and government electronics in 1994 as the IEEE standard 1386.1. The PCI interface is implemented using two 64-pin connectors for 32-bit support with an optional third to extend this to 64-bit PCI. A fourth 64-pin connector, also optional, is provided for user I/O. In the ensuing decade some major extensions were added to the PMC format though addition ANSI and VITA standards. One such extension is ANSI/VITA 20 which defines a conduction-cooled version of PMC for severe environments.
XMC (or Switched Mezzanine Card) owes its existence to the embedded computing community’s acceptance of a groundbreaking proposal in 2002 to standardize gigabit serial switched fabrics and defined in the ANSI/VITA 42.0 specification. The resulting VITA 42.3 XMC Mezzanine specification was a natural extension of the PCI standard by providing PCI Express support and adding new connectors to support gigabit serial interfaces and alternative I/O standards.
XMC has proven to be very successful, expanding past the base VITA 42.0 specification to include technologies such as Parallel RapidIO (ANSI/VITA 42.1), Serial RapidIO (ANSI/VITA42.2), and PCI Express (ANSI/VITA 42.3), to name the first three of a growing list. The PCI Express variant of XMC is by far the most common.
One of the key factors contributing to the popularity of XMC today is the widespread adoption of more sophisticated functions such as FPGA based processors for peripheral I/O functions, an application area where mezzanine cards like XMC are frequently employed. In addition, an increasing proportion of I/O functions are based on serial, rather than parallel interfaces which is exactly the reason the XMC specification was developed. Most new generation VME, VXS or VPX CPU or DSP format hosts are likely to have one or more XMC mezzanine sites.
Curtiss-Wright Defense Solutions offers a wide range of flexible, high performance XMC solutions, allowing system integrators to meet the demanding networking and I/O requirements of RADAR, EW, SIGINT, COMINT, ECM, ESM and C4ISR applications.