FPGA Mezzanine Cards – Like World Cup Football
With FPGA Mezzanine Cards you can get a high performance result but you must pay attention to the details
You want to build the best possible team for international competition and to do that you must be able to choose from a wide pool of players, coming from many different clubs. But highly skilled players are not enough; you need teamwork, strategy and the right blend to be effectively. You also need flexibility as new challenges are thrown at you. To do all this you need to understand the individual players and all the details; their strengths and weaknesses and when to use them. Get it right and you will achieve great results. Get it wrong and you’ll be history.
Parallels can be drawn with the FPGA Mezzanine Card format: it’s a mix and match format, but creating a successful overall solution requires selection of the right pieces, knowing their details and how to put them together. Get it right and you’ll achieve a high performance result. The decisions are more complex than those of the usual mezzanine approach but the rewards are higher.
The FPGA Mezzanine Card specification (VITA 57) is powerful: powerful because it provides a platform to couple high performance I/O, usually analog I/O, directly into an FPGA. This performance is built on the direct and intimate coupling of an FPGA and its I/O without standard busses or specific timing constraints getting in the way.
The FPGA Mezzanine Card specification, in the main, doesn’t even define the formal connectivity, only how you go about adding connectivity and its limits (maximum number of connections). Some infrastructure is defined, such as where the power supplies are connected (even some of those are optional) and mechanical details such as board outlines, mounting holes and the positioning of the FPGA Mezzanine Card connectors.
Putting the mechanics to one side, the FPGA Mezzanine Card specification defines:
- The maximum number of parallel I/O connections.
- The order in which the I/O is allocated if an FMC, or its host, do not have the maximum connectivity.
- The maximum number of High Speed Serial (HSS) ports. Set at up to 10 full duplex.
- Certain specific core power rails.
- A protocol which allows the host card to interrogate the FMC.
- Where clocks are to be provided.
Most importantly, the FPGA Mezzanine Card specification does not define busses or protocols such as PCIe or Ethernet, for example. Defining and formatting the I/O flow is left to the designer.
This freedom is at the heart of the FPGA Mezzanine Card standard’s ability to provide high performance, effective solutions – but it needs detailed knowledge and careful design management, which is why there is a strong preference that the FPGA host board and FPGA Mezzanine Card module are coordinated from one source.
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