Traditionally, CameraLink solutions use specific chipsets designed to implement ChannelLink, the physical interface associated with CameraLink. ChannelLink provides a parallel interface that is then multiplexed a few serial lines – and then de-multiplexed at the other end of the link if required. CameraLink is often used for high-performance imaging, usually frame grabbers.
The challenge is to provide a direct CameraLink interface to a Kintex-7 FPGA without the need for ChannelLink transceivers, thereby allowing an existing “generic” digital FPGA solution to be used. This provides greater flexibility as the hardware is no longer CameraLink specific and can also be used for other digital I/O schemes, such as LVDS in the future.
The CameraLink interface needs to support the Full, Medium, and Base I/O modes. Since the I/O is directly interfaced with a user-programmable FPGA, data processing can be combined with I/O for a high-performance imaging application.
Curtiss-Wright has previously supplied FPGA I/O cards with CameraLink/ChannelLink I/O modules along with CameraLink FPGA IP allowing customers to embed this IP into their FPGA-based application – with a high-speed DMA has driven PCIe/PCI-X interface for host interface and control.
Read about the solution Curtiss-Wright developed and the results achieved in our case study - download the case study to learn more.