The King is Dead; Long Live FPGA Digital Down Converters (DDC)
It’s the end of an era. The industry standard GC4016 narrow band Digital Down Converters (DDC) device has finally been withdrawn by Texas Instruments. Well, almost.
The final last time buy expired earlier this month, and final deliveries have yet to be made. Some may take this to mean the digital down converter function has fallen out of favor, but it is just the way the digital down converter function is now implemented has changed because of the high-speed data throughput needed by today’s applications. Today the digital down converter is usually implemented as a part of something else in the same way as dedicated Universal Asynchronous Receiver Transmitters (UARTS), disk controllers and even Central Processing Units (CPUs) have been absorbed into multi-function devices.
Modern digital down converters have gravitated into two platforms: the latest generation Analog to Digital converters (ADCs) and the application IP within FPGAs. Either solution positions the digital down converter exactly where it needs to be: the front end of the system where raw data needs to be unpicked to avoid overloading the CPUs or subsequent busses.
Digital down converters are perfect for applications such as Direction Finding (DF), SIGINT or Electronic Warfare (EW) where the system needs to be highly responsive, accurate and in the case of EW, low latency. This is because effective solutions need to know what the signals are, how to assess whether they are hostile, and where they are coming from with minimum fuss. Having the ability to extract data digitally at Radio Frequency (RF) speeds helps with this process and offers SWaP improvements by removing intermediate frequency (IF) stages completely to increase performance. In platforms such as UAVs, SWaP optimization is critical. Minimizing cards, even small form-factors such as VPX, is always beneficial as good RF digital down converters implemented in FPGAs provide a very flexible way to save.
So what’s next?