Digital Down Conversion (DDC) FPGA IP Cores

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Digital Down Conversion (DDC) FPGA IP cores are available supporting AMD Virtex/Kintex-7 FPGAs. The DDC family of IP cores support decimation from 2 to 64 in complex mode and from 2 to 32 in real mode. The DDC is available as embedded IP within a number of Curtiss-Wright ADC products or in a source format. The DDC supports the FusionXF development tools.

Benefits of the DDC products include reduced application development time, fully-tested and documented HDL components, east integration with other application HDL and complete Digital Down Converter (DDC) I/O. Curtiss-Wright offers the DDC001 as an IP package that users can integrate with their own application code. The DDC001 arrives with HDL source code, test bench and full user documentation. The toolchain used for creating the IP is AMD ISE 10.1.3 and ModelSim 6.3.

The Curtiss-Wright DDC001 is a Wideband Digital Down Converter (DDC). It delivers functionality similar to that of GC1012B from TI. It supports output bandwidth of Fs/4 to Fs/128 with a complex output and Fs/2 to Fs/64 with a real output. The DDC001 operates in excess of 250MHz in a -2 speed grade AMD Virtex-5 SX95T.

  • AMD Virtex-7 FPGA support
  • 16-bit input
  • NCO with 32-bit tuning word, 120dB SFDR
  • 18-bit or 24-bit coefficients
  • Four independent programmable coefficient sets
  • Up to 2560 filter taps
  • Complex or real outputs
  • Decimation of 2, 4, 8, 16, 32 or 64 (complex)
  • Decimation of 1, 2, 4, 8, 16 or 32 (real)
  • Output formatting to 16-bits or 24-bits
  • Output spectrum can be inverted or shifted by Fo/2
  • Modular design supporting customization for specific requirements e.g. more or fewer
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Digital Down Conversion (DDC) FPGA IP Cores

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