Why We Need Chips With Integrated RF Data Converters
A new Radio Frequency System-on-a-Chip (RFSoC) recently announced by Xilinx will bring better system performance, lower power requirements, a smaller form factor, and lower weight to defense and aerospace applications.
The RFSoC is an architectural breakthrough in chip design. It integrates the processor, FPGA, and analog-to-digital converter/digital-to-analog converter (ADC/DAC) on a single, fully programmable chip. The RFSoC was originally developed to address new requirements and challenges in 5G wireless networks. However, these same benefits can be applied to a range of defense and aerospace applications. And which system integrator isn’t looking to cut space, weight, and power — while improving performance?
Latency Improvements Are Key in Electronic Warfare
It’s pretty obvious that combining three chips into one significantly reduces space and weight requirements on the board. And it’s obvious why that’s important. But it’s the system performance improvements — specifically lower latency — that would arguably have the greatest benefit in defense and aerospace applications.
Latency is a major challenge for system integrators. While applications, such as radar, are less sensitive to latency, others, such as electronic warfare applications, cannot tolerate latency.
Analog to digital converter sampling rates and resolution requirements are at the heart of the latency challenge. The boards used in today’s defense and aerospace applications have separate processor, FPGA, and ADC chips. As sampling rates for data get faster and sampling resolutions get higher, more data has to be passed from the analog to digital converter to the FPGA. There are two ways to move all of this data:
- Use parallel processing, which enables efficient data transfer, but causes routing congestion on the board and may be limited due to connector pinout constraints.
- Use high-speed SerDes signals, which cuts down on the number of signals that have to be routed, but adds latency.
To relieve congestion on the board, most ADC vendors have been moving to serial data transfer using JESD204B. Hence, the latency issue. However, when the ADC is integrated with the FPGA as it is on the RFSoC, wide parallel processing becomes possible without having to route the connections on the board. For applications such as a digital RF memory (DRFM), which takes a signal in, manipulates the data, and sends it back out again, the latency improvements that this kind of processing enables are crucial.
Power Requirements Go Down, Channel Density Goes Up
Here’s a quick look at two other key benefits the RFSoC provides:
- Eliminating the ADC/DAC as a discrete component, and removing the need for an FPGA-to-analog interface dramatically reduces power requirements. In the press release announcing the disruptive, integrated design, Xilinx estimated a 50-75% power cut for 5G wireless applications.
- The RFSoC also supports a high number of input and output channels, increasing the density of analog channels that the FPGA can support. The high processing power that becomes available in the RFSoC gives system integrators new abilities to take advantage of these I/O channels.
Moving to Rugged Applications
The RFSoC addresses a key challenge in the low-latency, “sense and response” application space. By eliminating the ADC-FPGA and FPGA-DAC external interface, low latency is achieved without routing complexity as sampling rates and resolution continue to increase. Furthermore, increased channel densities are possible in many small form factors. All of which makes the new RFSoC ideal for defense and aerospace applications.