Showing 25 - 32 of 46
Air Beat

SWaP-Optimized: The Right Way to Add Advanced Surveillance Capabilities to Rotorcraft

Making the modern video equipment work together with the platform’s legacy systems can be costly and complex. The time and effort needed to integrate a myriad of legacy and modern video formats and resolutions can both add program risk and delay deployment.

10/31/2018
Military Embedded Systems

Milestone in Abstracting the Hardware: Realizing the Promise of FACE

With the wide adoption of FACE, system integrators can reap tremendous benefits in interoperability and cost.

10/17/2018
article

Pushing Airborne ISR Data Recorders to New Performance Heights

Paul Davis looks at how it’s now possible to design digital data recorders that can absorb upwards of 6 GB per second of streaming data, 400 percent more bandwidth then the fastest SFPDP recorder could handle.

04/30/2018
Military Embedded Systems

Introducing Gen 5 VPX

Ivan Straznicky looks at the introduction of Gen 5 VPX, the initial Gen 5 VPX protocols are expected to be 100 Gigabit Ethernet (100G-KR4) and Infiniband EDR [enhanced data rate).

03/21/2018
Military Embedded Systems

Zen and the Art of HPEC Software Debugging

Tammy Carter looks at how debugging tools are expanding the ability to produce quality and more robust software for HPEC systems.

09/18/2017
Avionics Magazine

Is This The Flight Data Recorder of the Future?

The Curtiss-Wright Fortress can function as a traditional FDR, cockpit voice recorder, datalink recorder or airborne image recorder, or a combination of the four. It also allows operators to use the data captured for predictive maintenance.

07/13/2017
Intelligent Aerospace

Lowering the Cost of Spacecraft Avionics with Radiation-Tolerant COTS Electronics

The risk of failure for avionics equipment on-board spacecraft due to radiation exposure is a critical issue for launchers, re-entry vehicles, space habitats and satellites

05/19/2017
Military Embedded Systems

Taking the Complexity Out of PCI Express Configuration to Optimize HPEC System Design

Performance is all about eliminating bottlenecks to minimize latency and maximize throughput. To maximize overall system performance requires the fastest, most efficient processor-to-processor data paths.

04/18/2017