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Use of GPGPU technology increases in aerospace and defense applications

April 19, 2016 | BY: Marc Couture

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Interest in the use of graphics processing unit (GPU) silicon for general purpose computing (GPGPU) in aerospace and defense applications has existed since the early 2000s. Early on, use was restricted to research SBIRs and IRADs. While some defense programs picked them up for deployment, most had concerns. From a program logistics point of view, there simply wasn’t enough support from silicon providers such as NVIDIA and AMD. The devices weren’t built with SWaP constraints in mind and the longevity of GPGPU device supply was always a concern. From a cost perspective, some applications high latency needs meant for an expensive solution. 

Today we are starting to see GPGPUs develop into a mainstay building block for deployable processing. Silicon providers have stepped up their game and have built internal business units to focus on the embedded industry, bringing a new level of support for defense applications. Small embedded modules are also becoming more readily available and kept around for a longer period of time, alleviating the stress of DMS issues.  

GPGPUs offer a wide variety of benefits for aerospace and defense depending on the specific application. From attacking some of the more intensive applications such as Processing-Exploitation-Dissemination (PED) for extreme SWaP-C reduction to countering threats in cognitive EW by offering much higher rates of adaptability, GPGPUs are popping up across the board. 

They provide an opportunity to simplify or even eliminate external interconnects by allowing all transactions to be kept within the silicon. Turning to a small number or even a single GPGPU brings a new level of locality to the table, saving on the code complexity associated with external DMA transfers, interrupts, doorbells and the like. They also offer a higher level of abstraction and readability compared to alternatives because of the programming languages they support.  

Download the white paper on GPGPUs in Defense to learn more about:  

  • GPGPU traction in defense apps 
  • Silicon providers focused on HPEC 
  • GPGPUs in Cognitive EW 
  • Ruggedizing TFLOPS 
  • Quick reaction with CUDA and OpenCL 

Author’s Biography

Marc Couture

Senior Product Manager for Intel, Power Architecture, and GPGPU based Digital Signal Processors

Marc Couture is the Senior Product Manager for Intel, Power Architecture, and GPGPU based Digital Signal Processors in the ISR Solutions group at Curtiss-Wright. He has worked in the Embedded COTS industry for over 20 years having specialized in High Performance Embedded Computing and RF/Microwave technologies. Marc is a graduate of the University of Massachusetts Dartmouth with a Masters of Science in Electrical Engineering.

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